llvm-svn: 191233

This mask is purely for debugging and testing.

llvm-svn: 191231

llvm-svn: 191226

a) Make sure we are emitting the correct section in our section labels
when we begin the module.
b) Make sure we are emitting the correct pubtypes section in the
presence of gnu pubtypes.
c) For C++ struct, union, class, and enumeration types are default
external.

llvm-svn: 191225

llvm-svn: 191214

The size of common symbols is now tracked correctly, so they can be listed in the arange section without needing knowledge of other following symbols.

.comm (and .lcomm) do not indicate to the system assembler any particular section to use, so we have to treat them as having no section.

Test case update to account for this.

llvm-svn: 191210

This is a small step that may enable some simplifications in producer
(DWARFContext) and consumer (DWARFCompileUnit and other places) by
making a more complete abstraction around the data and relocations for a
section. Small initial steps could include simple changes such as
passing the pair to DWARFCompileUnit's ctor rather than passing the data
and relocs separately. I don't intend to pursue any such changes
immediately, however.

The motivation for doing this now is that type unit dumping will need to
deal with these data+reloc pairs moreso than the existing dumping
support has needed to associate the data as type unit sections are named
the same (debug_types) and comdat group folded. So to implement dumping
and reloc handling we'll need a mapping of section->data+relocs.

llvm-svn: 191209

Revert 191122 - with extra checks we are allowed to vectorize math library
function calls.

Standard library indentifiers are reserved names so functions with external
linkage must not overrided them. However, functions with internal linkage can.

Therefore, we can vectorize calls to math library functions with a check for
external linkage and matching signature. This matches what we do during
SelectionDAG building.

llvm-svn: 191206

llvm-svn: 191203

Patch by Bradley Smith.

llvm-svn: 191202

Overflow doesn't affect the correctness of equalities. Computing this is cheap,
we just reuse the computation for the inbounds case and try to peel of more
non-inbounds GEPs. This pattern is unlikely to ever appear in code generated by
Clang, but SCEV occasionally produces it.

llvm-svn: 191200

Changes to MIPS SelectionDAG:
* Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single
  operation and implemented the DAG combines necessary to fold sign/zero
  extends into the extract.

llvm-svn: 191199

llvm-svn: 191198

llvm-svn: 191195

llvm-svn: 191194

Partially revert r191192: Fix -Wunused-variable error when assertions are disabled and -Werror is in use.

An unrelated change crept in because 'svn revert' isn't recursive by default.
The unrelated changes have been reverted.

llvm-svn: 191193

llvm-svn: 191192

[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD)

Note: There's a later patch on my branch that re-implements this to select
build_vector without the custom SelectionDAG nodes. The future patch avoids
the constant-folding problems stemming from the custom node (i.e. it doesn't
need to re-implement all the DAG combines related to BUILD_VECTOR).

Changes to MIPS specific SelectionDAG nodes:
* Added VSPLAT
    This is a special case of BUILD_VECTOR that covers the case the
    BUILD_VECTOR is a splat operation.
* Added VSPLATD
    This is a special case of VSPLAT that handles the cases when v2i64 is legal

llvm-svn: 191191

llvm-svn: 191180

llvm-svn: 191179

llvm-svn: 191178

This makes using array_pod_sort significantly safer. The implementation relies
on function pointer casting but that should be safe as we're dealing with void*
here.

llvm-svn: 191175

llvm-svn: 191172

[Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter.

llvm-svn: 191168

[Sparc] Clean up MOVcc instructions so that TableGen can encode them correctly. No functionality change intended.

llvm-svn: 191167

[Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended.

llvm-svn: 191166

Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.

Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.

This should fix PR15840.

llvm-svn: 191165

llvm-svn: 191164

Summary:
LLVM would crash when trying to come up with a relocation type for
assembly like:
movabsq $V@TPOFF, %rax

Instead, we say the relocation type is R_X86_64_TPOFF64.

Fixes PR17274.

Reviewers: dblaikie, nrieck, rafael

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1717

llvm-svn: 191163

llvm-svn: 191160

llvm-svn: 191158

Pre-increment loads are microcoded on the A2, and the address increment occurs
only after the load completes. As a result, the latency of the GPR address
update is an additional 2 cycles on top of the load latency.

llvm-svn: 191156

llvm-svn: 191154

SROA wants to convert any types of equivalent widths but it's not possible to
convert vectors of pointers to an integer scalar with a single cast. As a
workaround we add a bitcast to the corresponding int ptr type first. This type
of cast used to be an edge case but has become common with SLP vectorization.
Fixes PR17271.

llvm-svn: 191143

This reverts commit r191130.

llvm-svn: 191138

llvm-svn: 191136

llvm-svn: 191135

Allow binutils .type and .section directives to take the following
forms:
- @<type>
- %<type>
- "<type>"

llvm-svn: 191134

llvm-svn: 191133

In AVX 256bit vectors are valid vectors and therefore the Type Legalizer doesn't
split the VSELECT and SETCC nodes. AVX only supports MIN/MAX on 128bit vectors
and this fix enables vector splitting for this special case in the X86 DAG
Combiner.

This fix is related to PR16695, PR17002, and <rdar://problem/14594431>.

llvm-svn: 191131