llvm-svn: 38500

in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.

llvm-svn: 38478

register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.

llvm-svn: 38471

zero if they see a target triple they don't understand.

llvm-svn: 38463

llvm-svn: 37965

llvm-svn: 37962

llvm-svn: 37961

llvm-svn: 37960

llvm-svn: 37959

llvm-svn: 37940

llvm-svn: 37932

llvm-svn: 37931

llvm-svn: 37930

llvm-svn: 37926

llvm-svn: 37923

llvm-svn: 37917

llvm-svn: 37915

llvm-svn: 37914

Almost all occurrences of "bytecode" in the sources have been eliminated.

llvm-svn: 37913

llvm-svn: 37911

llvm-svn: 37898

llvm-svn: 37897

llvm-svn: 37896

Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.

llvm-svn: 37895

llvm-svn: 37894

llvm-svn: 37893

- Added two variants of PredicateOperand: ImmutablePredicateOperand, whose predicate does not change after isel; PredicateDefOperand, which represent a predicate defintion operand.

llvm-svn: 37892

llvm-svn: 37891

their names are changed.

llvm-svn: 37876

llvm-svn: 37866

Still need to have JIT generate this code.

llvm-svn: 37863

llvm-svn: 37853

model to include f32 variants.  Some factoring
improvments forthcoming.

llvm-svn: 37847

the recent lowering changes, this allows types like <4 x double> to
be returned, using two vector registers.

llvm-svn: 37844

llvm-svn: 37801

llvm-svn: 37790

llvm-svn: 37786

llvm-svn: 37784

llvm-svn: 37768

llvm-svn: 37756