llvm-svn: 50607

llvm-svn: 50604

Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code.

llvm-svn: 50601

llvm-svn: 50600

llvm-svn: 50596

llvm-svn: 50591

llvm-svn: 50590

llvm-svn: 50586

llvm-svn: 50582

llvm-svn: 50578

llvm-svn: 50575

Not safe folding a load + FsXORPSrr into FsXORPSrm. It's loading a FR64 value but the load folding variant expects a 16-byte aligned address.

llvm-svn: 50574

llvm-svn: 50564

llvm-svn: 50562

llvm-svn: 50561

llvm-svn: 50558

from x86-64 calling convention work.

llvm-svn: 50545

fixes the 254.gap regression on x86 and the 403.gcc regression on x86-64.

llvm-svn: 50537

ffastmath mode.  This fixes rdar://5902801, a miscompilation
of gcc.dg/builtins-8.c.

Bill, please pull this into Tak.

llvm-svn: 50523

2) Return NULL instead of false in several places for tidiness.
3) fix a bug optimizing  sprintf(p, "%c", x)

llvm-svn: 50521

a FunctionPass.  This makes it simpler, fixes dozens of bugs, adds
a couple of minor features, and shrinks is considerably: from
2214 to 1437 lines.

llvm-svn: 50520

llvm-svn: 50483

Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.

Initial PowerPC tail call implementation:

Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).  
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if 
  caller and callee are fastcc
  call is a tail call (in tail call position, call followed by ret)
  no variable argument lists or byval arguments
  option -tailcallopt is enabled
Supported:
 * non pic tail calls on linux/darwin
 * module-local tail calls on linux(PIC/GOT)/darwin(PIC)
 * inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.

A test checking the argument lowering behaviour on x86-64 was added.

llvm-svn: 50477

llvm-svn: 50475

llvm-svn: 50473

to instcombine.

llvm-svn: 50472

llvm-svn: 50465

llvm-svn: 50464

llvm-svn: 50463

fixes are target-specific lowering of frame indices, fix constants generated
for the FSMBI instruction, and fixing SPUTargetLowering::computeMaskedBitsFor-
TargetNode().

llvm-svn: 50462

DAG.UpdateNodeOperands() is called before (not after) the call to
TLI.LowerOperation().

llvm-svn: 50461

targets.

llvm-svn: 50451

Revert r50441.  The original code was correct.  Add some more comments so that I don't make the same mistake in the future.

llvm-svn: 50446

we were checking for it in the wrong order.  This caused a miscompilation because the
return slot optimization assumes that the call it is dealing with is NOT a memcpy.

llvm-svn: 50444

llvm-svn: 50442

of this was suggested by Chris.

llvm-svn: 50441

llvm-svn: 50437

llvm-svn: 50436

llvm-svn: 50433

This fixes the second half of PR2262

llvm-svn: 50430