llvm-svn: 104974

make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.

llvm-svn: 104967

an alloca() or an llvm.stackrestore(). rdar://8031573

llvm-svn: 104900

llvm-svn: 104661

Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419

t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.

llvm-svn: 104115

Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.

llvm-svn: 104111

Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.

llvm-svn: 104102

Obvious in retrospect but not fun to debug.

llvm-svn: 103969

llvm-svn: 103903

Temporary emit it as raw bytes until it will be added to binutils as well.

llvm-svn: 103878

llvm-svn: 103459

need them.

llvm-svn: 98937

instructions for ld/st with writeback, the flag is completely redundant.

llvm-svn: 98643

writebacks to the address register.  This gets rid of the hack that the
first register on the list was the magic writeback register operand.  There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand.  The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other.  This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.

llvm-svn: 98409

operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.

llvm-svn: 98172

MULS <Rdm>, <Rn>, <Rdm>

according to A8.6.105 MUL Encoding T1.

llvm-svn: 97675

SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.

llvm-svn: 97573

llvm-svn: 97348

WFI, SEV, SETEND.

llvm-svn: 97149

llvm-svn: 97105

llvm-svn: 97098

126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.

llvm-svn: 96822

llvm-svn: 96393

llvm-svn: 96388

llvm-svn: 95884

tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.

llvm-svn: 95686

llvm-svn: 95603

llvm-svn: 94627

cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.

llvm-svn: 94119

the various MOV (register) instructions (16-bit Thumb), including tBRIND (the
indirect branch).  Instead of '1', it should be specified as '?', because GPR
only specifies the register class, which includes both hi-and-lo registers.

llvm-svn: 93759

the disassembler can properly decode Load/Store register/immediate instructions.

llvm-svn: 93471

llvm-svn: 93349

It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.

llvm-svn: 93280

Certain Thumb instructions require only SP (e.g. tSTRspi).

llvm-svn: 91944

llvm-svn: 91571

bytes of Inst to 0x0000 for the benefit of the Thumb decoder.

llvm-svn: 91496

llvm-svn: 91434

llvm-svn: 90246

llvm-svn: 89478