DWARF requires frame moves be specified at specific times. If you have a
prologue like this:

__Z3fooi:
Leh_func_begin1:
LBB1_0: ## entry
       pushl   %ebp
Llabel1:
       movl    %esp, %ebp
Llabel2:
       pushl   %esi
Llabel3:
       subl    $20, %esp
       call    "L1$pb"
"L1$pb":
       popl    %esi

The "pushl %ebp" needs a table entry specifying the offset. The "movl %esp,
%ebp" makes %ebp the new stack frame register, so that needs to be specified in
DWARF. And "pushl %esi" saves the callee-saved %esi register, which also needs
to be specified in DWARF.

Before, all of this logic was in one method. This didn't work too well, because
as you can see there are multiple FDE line entries that need to be created.

This fix creates the "MachineMove" objects directly when they're needed; instead
of waiting until the end, and losing information.

There is some ugliness where we generate code like this:


LBB22_0:	## entry
	pushl	%ebp
Llabel280:
	movl	%esp, %ebp
Llabel281:
Llabel284:
	pushl	%ebp  <----------
	pushl	%ebx
	pushl	%edi
	pushl	%esi
Llabel282:
	subl	$328, %esp

Notice the extra "pushl %ebp". If we generate a "machine move" instruction in
the FDE for that pushl, the linker may get very confused about what value %ebp
should have when exitting the function. I.e., it'll give it the value %esp
instead of the %ebp value from the first "pushl". Not to mention that, in this
case, %ebp isn't modified in the function (that's a separate bug). I put a small
hack in to get it to work. It might be the only solution, but should be
revisited once the above case is fixed.

llvm-svn: 75047

llvm-svn: 75046

Will convert assert(0) that don't have abort() to LLVM_UNREACHABLE in a later
commit.

llvm-svn: 75045

Finish converting lib/Target.

llvm-svn: 75043

llvm-svn: 75040

llvm-svn: 75039

llvm-svn: 75038

llvm-svn: 75037

llvm-svn: 75036

Added ARMBaseRegisterInfo.cpp to lib/Target/ARM/CMakeLists.txt

llvm-svn: 75035

Support MDNode forward reference.

llvm-svn: 75031

to a loop deletion more thorough. Don't prune the def-use tree search at
instructions that don't have SCEVs computed, because an instruction with
a user that has a computed SCEV may itself lack a computed SCEV.  Also,
remove loop-related values from the ValuesAtScopes and
ConstantEvolutionLoopExitValues maps as well.

This fixes a regression in 483.xalancbmk.

llvm-svn: 75030

This way ScalarEvolution can examine the loop to determine what state
it needs to update, if it chooses.

llvm-svn: 75029

Also remove trailing semicolon.

llvm-svn: 75027

llvm-svn: 75025

llvm-svn: 75024

llvm-svn: 75023

llvm-svn: 75022

llvm-svn: 75020

llvm-svn: 75019

cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)

llvm-svn: 75018

llvm-svn: 75017

llvm-svn: 75016

llvm-svn: 75015

llvm-svn: 75012

llvm-svn: 75011

Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.

llvm-svn: 75010

and cases alphabetically.  No functionality change.

llvm-svn: 75001

llvm-svn: 75000

Fixed build, requires std header before using std::string

llvm-svn: 74995

Mark sublw_cc and subfw_cc as Terminator insns so that they are part of the terminator insns for a basic block alongwith branch insns. This way a copy is not getting inserted between cmp and branch during PHIElimination disturbing the status flags.

llvm-svn: 74992

these instructions, no autoupgrade or backwards compatibility support is
provided.

llvm-svn: 74991

Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.

llvm-svn: 74988

llvm-svn: 74985

llvm-svn: 74982

llvm-svn: 74981

llvm-svn: 74980

functionality change.

llvm-svn: 74979

VSETCC must define all bits, which is different than it was documented
to before.  Since all targets that implement VSETCC already have this
behavior, and we don't optimize based on this, just change the 
documentation.  We now get nice code for vec_compare.ll

llvm-svn: 74978

llvm-svn: 74977