llvm-svn: 125987

llvm-svn: 125986

LLVM_INCLUDE_TESTS:=OFF, which may no longer be necessary for all I know.

llvm-svn: 125985

Do not lose debug info of an inlined function argument even if the argument is only used through GEPs.
This time with a fix that avoids using invalidated DenseMap iterator.

llvm-svn: 125984

llvm-svn: 125983

llvm-svn: 125982

need to be pulled out of the pass manager when the user specifies 
-fno-builtin.  It can intelligently determine which libcalls to
optimize based on what is enabled in TargetLibraryInfo.  This 
allows -fno-builtin-foo to work someday.

llvm-svn: 125981

All new virtual registers created for spilling or splitting point back to their original.

llvm-svn: 125980

turn off all builtin optimizations.

llvm-svn: 125979

llvm-svn: 125978

that was ignored in a few places (most notably, code
completion). Introduce Selector::getNameForSlot() for the common case
where we only care about the name. Audit all uses of
getIdentifierInfoForSlot(), switching many over to getNameForSlot(),
fixing a few crashers.

Fixed <rdar://problem/8939352>, a code-completion crasher.

llvm-svn: 125977

Without this I get:
--
-- Generating done
CMake Error: Unknown Target referenced : check.deps
CMake Error: Target: check-all depends on unknown target: check.deps
--

llvm-svn: 125976

Add code to emulate LDRB (literal) Arm instruction.

llvm-svn: 125975

to hack on memset, memcpy etc.

llvm-svn: 125974

llvm-svn: 125973

llvm-svn: 125972

target triple.  This would be a decent place to add -fno-builtin
info for example.

llvm-svn: 125971

with a triple.

llvm-svn: 125970

llvm-svn: 125969

llvm-svn: 125968

The rewriter works almost identically to -rewriter=trivial, except it also
eliminates any identity copies.

This makes the new register allocators independent of VirtRegRewriter.cpp which
will be going away at the same time as RegAllocLinearScan.

llvm-svn: 125967

Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for fixed-length instruction encodings.
A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks
provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen
like the existing disassembly emitters do.

The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove
some of the hacks the old one introduced to tblgen.

llvm-svn: 125966

query about available library functions.  For now this just has 
memset_pattern16, which exists on darwin, but it can be extended for a 
bunch of other things in the future.

llvm-svn: 125965

llvm-svn: 125964

llvm-svn: 125963

llvm-svn: 125962

Plus add a helper method ReadCoreReg(uint32_t regnum, bool *success) to simplify
coding a bit.

llvm-svn: 125961

llvm-svn: 125960

Add code to emulate LDRB (immediate, Thumb) instruction.

llvm-svn: 125959

llvm-svn: 125958

No functionality change.

llvm-svn: 125957

parallel with the rest of the tools directory as it depends on Clang.

llvm-svn: 125956

llvm-svn: 125949

testcases for the disassembler to make sure it still works for "msr".

llvm-svn: 125948

Plus add macro definitions for APSR_C and APSR_V to simplify code.

llvm-svn: 125947

scalar types. // rdar://7761305

llvm-svn: 125946

Add code to emulate LDR (register) Arm instruction.

llvm-svn: 125945

patch by Amit Kulkarni!

llvm-svn: 125944

llvm-svn: 125943

llvm-svn: 125845