llvm-svn: 17637

move instructions for the register allocator to coalesce.

llvm-svn: 17608

llvm-svn: 17583

llvm-svn: 17547

llvm-svn: 17544

llvm-svn: 17488

llvm-svn: 17484

int test(int x) { return 32768 - x; }

Fixed by teaching the function that checks a constant's validity to be used
as an immediate argument about subtract-from instructions.

llvm-svn: 17476

llvm-svn: 17464

This method is really a gross hack, but at least we can make it work on
the targets we support right now.

This bug fix stops a crash in a testcase reduced from 176.gcc

llvm-svn: 17443

Added gross hacks such as creating my own def-use map, and picking on Instruction that I can add all my TmpInstructions to its MCFI.

llvm-svn: 17441

llvm-svn: 17431

llvm-svn: 17406

llvm-svn: 17359

Fixed issue with generating the partial order. It now adds the nodes not in recurrences in sets for each connected component.

llvm-svn: 17351

llvm-svn: 17347

llvm-svn: 17346

llvm-svn: 17286

Move destructor out of line to avoid vtable emission in every file that includes the header.  Thanks to sabre.

llvm-svn: 17278

llvm-svn: 17275

SkeletonGenRegisterInfo.h.inc

llvm-svn: 17245

from PowerPCFrameInfo.h to PowerPCAsmPrinter.cpp where it is actually
needed.

llvm-svn: 17244

llvm-svn: 17240

llvm-svn: 17235

allow and const, 0 to be incorrectly codegen'd into a rlwinm instruction.

llvm-svn: 17234

llvm-svn: 17230

llvm-svn: 17221

llvm-svn: 17216

destination basic block are copied.

llvm-svn: 17212

by the recently committed rlwimi.ll test file.  Also commit initial code
for bitfield extract, although it is turned off until fully debugged.

llvm-svn: 17207

* Stop the confusion of using rv and Addr for global addresses: just use rv

llvm-svn: 17195

llvm-svn: 17193

* Convert register numbers from their opcode value to the real value, e.g.
  PPC::R1 => 1 and PPC::F1 => 1
* Add correct handling of loading of global values which are PC-relative --
  implement ha16() and lo16()

llvm-svn: 17190

be listed second as that is how the instructions are usually created (and is the
correct asm syntax) so that it's assembled correctly from its constituents

llvm-svn: 17183

The decimal value given in the manual (8 or 9) really needs to be multiplied by
a factor of 32 because of the group of 5 zero bits after the register code.

llvm-svn: 17182

llvm-svn: 17181

llvm-svn: 17180

llvm-svn: 17178

as the shift amount operand to a shift instruction.  This was causing us to
emit unnecessary clear operations for code such as:
int foo(int x) { return 1 << x; }

llvm-svn: 17175

llvm-svn: 17173