query about available library functions.  For now this just has 
memset_pattern16, which exists on darwin, but it can be extended for a 
bunch of other things in the future.

llvm-svn: 125965

llvm-svn: 125949

testcases for the disassembler to make sure it still works for "msr".

llvm-svn: 125948

llvm-svn: 125832

llvm-svn: 125805

Validate encoding of leave in 64bit mode.

llvm-svn: 125795

[AVX] Recorganize X86ShuffleDecode into its own library
(LLVMX86Utils.a) to break cyclic library dependencies between
LLVMX86CodeGen.a and LLVMX86AsmParser.a.  Previously this code was in
a header file and marked static but AVX requires some additional
functionality here that won't be used by all clients.  Since including
unused static functions causes a gcc compiler warning, keeping it as a
header would break builds that use -Werror.  Putting this in its own
library solves both problems at once.

llvm-svn: 125765

these patterns.

llvm-svn: 125759

No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way.

llvm-svn: 125747

llvm-svn: 125746

llvm-svn: 125738

llvm-svn: 125702

llvm-svn: 125681

other getNode() methods.  Radar 9002173.

llvm-svn: 125665

llvm-svn: 125660

llvm-svn: 125659

llvm-svn: 125658

llvm-svn: 125629

Some single precision VFP instructions may be executed on NEON pipeline, but not double precision ones.

llvm-svn: 125624

This is necessary to avoid a crash in certain tangled situations where a kill
flag is first correctly moved to a merged instruction, and then needs to be
moved again:

  STR %R0, a...
  STR %R0<kill>, b...

First becomes:

  STR %R0, b...
  STM a, %R0<kill>, ...

and then:

  STM a, %R0, ...
  STM b, %R0<kill>, ...

We can now remove the kill flag from the merged STM when needed. 8960050.

llvm-svn: 125591

llvm-svn: 125563

llvm-svn: 125534

llvm-svn: 125521

- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
  from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
  wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.

llvm-svn: 125489

have their low bits set to zero.  This allows us to optimize
out explicit stack alignment code like in stack-align.ll:test4 when
it is redundant.

Doing this causes the code generator to start turning FI+cst into
FI|cst all over the place, which is general goodness (that is the
canonical form) except that various pieces of the code generator
don't handle OR aggressively.  Fix this by introducing a new
SelectionDAG::isBaseWithConstantOffset predicate, and using it
in places that are looking for ADD(X,CST).  The ARM backend in
particular was missing a lot of addressing mode folding opportunities
around OR.

llvm-svn: 125470

These are just FXSAVE and FXRSTOR with REX.W prefixes.  These versions use
64-bit pointer values instead of 32-bit pointer values in the memory map they
dump and restore.

llvm-svn: 125446

llvm-svn: 125444

llvm-svn: 125438

Teach the AsmMatcher handling to distinguish between an error custom-parsing
an operand and a failure to match. The former should propogate the error
upwards, while the latter should continue attempting to parse with
alternative matchers.

Update the ARM asm parser accordingly.

llvm-svn: 125426

This avoids moving each element to the integer register file and calling __divsi3 etc. on it.

llvm-svn: 125402

llvm-svn: 125363

This
define float @foo(float %x, float %y) nounwind readnone {
entry:
  %0 = tail call float @copysignf(float %x, float %y) nounwind readnone
  ret float %0
}

Was compiled to:
    vmov     s0, r1
    bic      r0, r0, #-2147483648
    vmov     s1, r0
    vcmpe.f32    s0, #0
    vmrs         apsr_nzcv, fpscr
    it           lt
    vneglt.f32   s1, s1
    vmov         r0, s1
    bx           lr

This fails to copy the sign of -0.0f because it's lost during the float to int
conversion. Also, it's sub-optimal when the inputs are in GPR registers.

Now it uses integer and + or operations when it's profitable. And it's correct!
    lsrs    r1, r1, #31
    bfi     r0, r1, #31, #1
    bx      lr
rdar://8984306

llvm-svn: 125357

[AVX] Implement 256-bit vector lowering for SCALAR_TO_VECTOR.  This
largely completes support for 128-bit fallback lowering for code that
is not 256-bit ready.

llvm-svn: 125315

Fix a lot of o32 CC issues and add a bunch of tests. Patch by Akira Hatanaka with some small modifications by me.

llvm-svn: 125292

[AVX] Implement 256-bit vector lowering for EXTRACT_VECTOR_ELT.

llvm-svn: 125284

llvm-svn: 125279

[AVX] Implement 256-bit vector lowering for INSERT_VECTOR_ELT.

llvm-svn: 125187

llvm-svn: 125186

Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it).  This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.

llvm-svn: 125127

[AVX] Implement BUILD_VECTOR lowering for 256-bit vectors.  For
anything but the simplest of cases, lower a 256-bit BUILD_VECTOR by
splitting it into 128-bit parts and recombining.

llvm-svn: 125105