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  1. Mar 04, 2014
    • David Blaikie's avatar
      DebugInfo: Emit only the declaration of a class template that has an explicit... · 0e716b42
      David Blaikie authored
      DebugInfo: Emit only the declaration of a class template that has an explicit instantiation declaration (& always emit such a type when there's an explicit instantiation definition)
      
      We should only have this optimization fire when the explicit
      instantiation definition would cause at  least one member function to be
      emitted, thus ensuring that even a compiler not performing this
      optimization would still emit the full type information elsewhere.
      
      But we should also pessimize output still by always emitting the
      definition when the explicit instantiation definition appears so that at
      some point in the future we can depend on that information even when no
      code had to be emitted in that TU. (this shouldn't happen very often,
      since people mostly use explicit spec decl/defs to reduce code size -
      but perhaps one day they could use it to explicitly reduce debug info
      size too)
      
      This was worth about 2% for Clang and LLVM - so not a huge win, but a
      win. It looks really great for simple STL programs (include <string> and
      just declare a string - 14k -> 1.4k of .dwo)
      
      llvm-svn: 202769
      0e716b42
    • Chad Rosier's avatar
      [AArch64] This is a work in progress to provide a machine description · fe452905
      Chad Rosier authored
      for the Cortex-A53 subtarget in the AArch64 backend.
      
      This patch lays the ground work to annotate each AArch64 instruction
      (no NEON yet) with a list of SchedReadWrite types. The patch also
      provides the Cortex-A53 processor resources, maps those the the default
      SchedReadWrites, and provides basic latency. NEON support will be added
      in a subsequent patch with proper forwarding logic.
      
      Verification was done by setting the pre-RA scheduler to linearize to
      better gauge the effect of the MIScheduler. Even without modeling the
      forward logic, the results show a modest improvement for Cortex-A53.
      
      Reviewers: apazos, mcrosier, atrick
      Patch by Dave Estes <cestes@codeaurora.org>!
      
      llvm-svn: 202767
      fe452905
  2. Mar 03, 2014
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