I still don't know how to refer to the fixed operands symbolically. I
plan to look into it.

llvm-svn: 194529

argument was not being passed in $f14.
 

llvm-svn: 194522

llvm-svn: 194515

The system LDM and STM instructions can't usually writeback to the base
register. The one exception is when an LDM is actually an exception-return
(i.e. contains PC in the register list).

(There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there
is no positive test).

rdar://problem/15223374

llvm-svn: 194512

 

llvm-svn: 194511

 

llvm-svn: 194510

copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

llvm-svn: 194501

llvm-svn: 194500

We already know how to fold a reload from a frameindex without
analyzing the load instruction. Generalize this to handle any
frameindex load. This streamlines the logic for rematerializing loads
from stack arguments. As a side effect, it allows stackmaps to record
a stack argument location without spilling it.

Verified no effect on codegen for llvm test-suite.

llvm-svn: 194497

llvm-svn: 194484

Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier:
  asm ("ldi.w %w0, 1", "=f"(result));

Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended
output. This is a consequence of differences in the internal handling of
the registers in each compiler. To be source-compatible between the
compilers, users must use the 'w' print-modifier.

MSA registers (including control registers) are supported in clobber lists.

llvm-svn: 194476

llvm-svn: 194472

llvm-svn: 194471

llvm-svn: 194470

[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics)

llvm-svn: 194469

llvm-svn: 194466

ATOMIC_FENCE is lowered to a compiler barrier which is codegen only. There
is no need to emit an instructions since the XCore provides sequential
consistency.

Original patch by Richard Osborne

llvm-svn: 194464

llvm-svn: 194463

Print the range of registers used with a single letter prefix.
This better matches what the shader compiler produces and
is overall less obnoxious than concatenating all of the
subregister names together.

Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1,
it will print s[0:1] and so on.

There doesn't appear to be a straightforward way
to get the actual register info in the InstPrinter,
so this parses the generated name to print with the
new syntax.

The required test changes are pretty nasty, and register
matching regexes are now worse. Since there isn't a way to
add to a variable in FileCheck, some of the tests now don't
check the exact number of registers used, but I don't think that
will be a real problem.

llvm-svn: 194443

This has no material effect at this time since we don't have a direct
object emitter for mips16 and the assembler can't tell them apart. I
place a comment "16 bit inst" for those so that I can tell them apart in the
output. The constant island pass has only been minimally changed to allow
this. More complete branch work is forthcoming but this is the first
step.

llvm-svn: 194442

X86AsmPrinter::EmitInstruction, rather than X86MCInstLower::Lower.

The aim is to improve the reusability of the X86MCInstLower class by making it
more function-like. The X86::MORESTACK_RET_RESTORE_R10 pseudo broke the
function model by emitting an extra instruction to the MCStreamer attached to
the AsmPrinter.

The patch should have no impact on generated code. 
 

llvm-svn: 194431

Fixes <rdar://15432754> [JS] Assertion: "Folded a def to a non-store!"

The primary purpose of anyregcc is to prevent a patchpoint's call
arguments and return value from being spilled. They must be available
in a register, although the calling convention does not pin the
register. It's up to the front end to avoid using this convention for
calls with more arguments than allocatable registers.

llvm-svn: 194428

llvm-svn: 194425

the floating point register mode.
 

llvm-svn: 194423

llvm-svn: 194416

llvm-svn: 194410

llvm-svn: 194409

source operands, a vector, an element to insert, and a shift amount.

llvm-svn: 194406

llvm-svn: 194394

On non-Darwin PPC systems, we currently strip off the register name prefix
prior to instruction printing. So instead of something like this:

  mr r3, r4

we print this:

  mr 3, 4

The first form is the default on Darwin, and is understood by binutils, but not
yet understood by our integrated assembler. Once our integrated-as understands
full register names as well, this temporary option will be replaced by tying
this functionality to the verbose-asm option. The numeric-only form is
compatible with legacy assemblers and tools, and is also gcc's default on most
PPC systems. On the other hand, it is harder to read, and there are some
analysis tools that expect full register names.

llvm-svn: 194384

This causes issues with virtual registers.  We will likely need
to fix TailDuplicate in the future, or introduce a new version
that plays nicely with vregs.

llvm-svn: 194373

Instructions taking a vector list (e.g. "ld2 {v0.2d, v1.d2}, [x0]") need a
special register-class to deal with the constraints, and C++ code to support
selection. However, that C++ code can be made reasonably uniform to simplify
the selection process. Hence this patch.

No functionality change, so no tests.

llvm-svn: 194361

llvm-svn: 194340

llvm-svn: 194339

Still need to finish the branch part. Still lots more review of the code,
clean up and testing. 

llvm-svn: 194337

llvm-svn: 194335

This commit cleans up some comments in ARMBuildAttrs.h.
Besides, this commit fixes an error related to AllowWMMXv1
and AllowWMMXv2 (although they are not used currently.)

llvm-svn: 194327

formal arguments on the stack and stores created afterwards. We need this to
ensure tail call optimized function calls do not write over the argument area
of the stack before it is read out.
 

llvm-svn: 194309

This patch moves the jump address materialization inside the noop slide. This
enables patching of the materialization itself or its complete removal. This
patch also adds the ability to define scratch registers that can be used safely
by the code called from the patchpoint intrinsic. At least one scratch register
is required, because that one is used for the materialization of the jump
address. This patch depends on D2009.

Differential Revision: http://llvm-reviews.chandlerc.com/D2074

Reviewed by Andy

llvm-svn: 194306

The idea of the AnyReg Calling Convention is to provide the call arguments in
registers, but not to force them to be placed in a paticular order into a
specified set of registers. Instead it is up tp the register allocator to assign
any register as it sees fit. The same applies to the return value (if
applicable).

Differential Revision: http://llvm-reviews.chandlerc.com/D2009

Reviewed by Andy

llvm-svn: 194293