- Oct 04, 2011
-
-
Jim Grosbach authored
llvm-svn: 141117
-
Jim Grosbach authored
llvm-svn: 141115
-
Jim Grosbach authored
llvm-svn: 141114
-
Jim Grosbach authored
llvm-svn: 141113
-
Jim Grosbach authored
llvm-svn: 141111
-
Jim Grosbach authored
llvm-svn: 141110
-
Jim Grosbach authored
llvm-svn: 141108
-
David Greene authored
Add a test to do list manipulation and pass the result as arguments. This tests the new list element operator resolve code and provides an example of using list manipulation to do instruction pattern substitution. llvm-svn: 141102
-
Jim Grosbach authored
llvm-svn: 141099
-
Jim Grosbach authored
llvm-svn: 141096
-
David Dean authored
llvm-svn: 141092
-
Craig Topper authored
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. llvm-svn: 141065
-
Andrew Trick authored
This handles the case in which LSR rewrites an IV user that is a phi and splits critical edges originating from a switch. Fixes <rdar://problem/6453893> LSR is not splitting edges "nicely" llvm-svn: 141059
-
Andrew Trick authored
llvm-svn: 141049
-
Jim Grosbach authored
llvm-svn: 141047
-
Jim Grosbach authored
llvm-svn: 141046
-
Jim Grosbach authored
llvm-svn: 141038
-
- Oct 03, 2011
-
-
Akira Hatanaka authored
llvm-svn: 141030
-
Akira Hatanaka authored
llvm-svn: 141029
-
Akira Hatanaka authored
llvm-svn: 141028
-
Jim Grosbach authored
llvm-svn: 141025
-
Akira Hatanaka authored
llvm-svn: 141024
-
Jim Grosbach authored
llvm-svn: 141022
-
Akira Hatanaka authored
llvm-svn: 141017
-
Jim Grosbach authored
llvm-svn: 141010
-
Craig Topper authored
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
-
Rafael Espindola authored
llvm-svn: 141001
-
Craig Topper authored
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode. llvm-svn: 140997
-
Craig Topper authored
llvm-svn: 140994
-
Nick Lewycky authored
logic by David Meyer revealed this bug. llvm-svn: 140992
-
Torok Edwin authored
llvm-svn: 140991
-
Nick Lewycky authored
llvm-svn: 140980
-
Nick Lewycky authored
llvm-svn: 140979
-
- Oct 02, 2011
-
-
Craig Topper authored
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. llvm-svn: 140974
-
Craig Topper authored
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344. llvm-svn: 140971
-
Nick Lewycky authored
r140966. llvm-svn: 140969
-
- Oct 01, 2011
-
-
Craig Topper authored
llvm-svn: 140955
-
Craig Topper authored
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. llvm-svn: 140954
-
Bill Wendling authored
llvm-svn: 140904
-
Bill Wendling authored
llvm-svn: 140903
-