llvm-svn: 62180

llvm-svn: 62179

Use DebugInfo interface to lower dbg_* intrinsics.

llvm-svn: 62127

suggested by Chris.

llvm-svn: 62099

llvm-svn: 62024

llvm-svn: 61991

llvm-svn: 61972

the same formatting as their corresponding SSE2 instructions, for
consistency.

llvm-svn: 61971

Convert DwarfWriter into a pass.
Now Users request DwarfWriter through getAnalysisUsage() instead of creating an instance of DwarfWriter object directly.

llvm-svn: 61955

into their left operand, rather than their right. Do this
by commuting the operands and inverting the condition.

llvm-svn: 61842

llvm-svn: 61841

llvm-svn: 61836

X86_COND_B and X86_COND_AE, respectively.

llvm-svn: 61835

converted to LEA64_32r in x86's convertToThreeAddress. This
replaces code like this:
   movl  %esi, %edi
   inc   %edi
with this:
   lea   1(%rsi), %edi
which appears to be beneficial.

llvm-svn: 61830

llvm-svn: 61765

llvm-svn: 61715

squash warnings.

llvm-svn: 61707

llvm-svn: 61686

llvm-svn: 61603

llvm-svn: 61602

Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.

llvm-svn: 61557

llvm-svn: 61556

Use movaps / movd to extract vector element 0 even with sse4.1. It's still cheaper than pextrw especially if the value is in memory.

llvm-svn: 61555

promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType.  In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).

llvm-svn: 61542

Darwin doesn't. Make this optional for platforms.

llvm-svn: 61484

llvm-svn: 61426

llvm-svn: 61425

llvm-svn: 61424

llvm-svn: 61423

llvm-svn: 61420

about other platforms.

llvm-svn: 61415

a symbolic constant. This is unlikely to be intentional, but it
shouldn't crash the compiler.

llvm-svn: 61408

llvm-svn: 61407

llvm-svn: 61404

llvm-svn: 61400

llvm-svn: 61392

This removes all the _8, _16, _32, and _64 opcodes and replaces each
group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode
is now used to carry the size information. In tablegen, the size-specific
opcodes are replaced by size-independent opcodes that utilize the
ability to compose them with predicates.

This shrinks the per-opcode tables and makes the code that handles
atomics much more concise.

llvm-svn: 61389

Fixed lowering of v8i16 shuffles for v8i16 when we fall back to extract/insert.

llvm-svn: 61365

llvm-svn: 61356

constant shift count that doesn't fit in the shift instruction's
immediate field. This fixes PR3242.

llvm-svn: 61281