llvm-svn: 12849

llvm-svn: 12848

If the source of the cast is a load, we can just use the source memory location,
without having to create a temporary stack slot entry.

Before we code generated this:

double %int(int* %P) {
        %V = load int* %P
        %V2 = cast int %V to double
        ret double %V2
}

into:

int:
        sub %ESP, 4
        mov %EAX, DWORD PTR [%ESP + 8]
        mov %EAX, DWORD PTR [%EAX]
        mov DWORD PTR [%ESP], %EAX
        fild DWORD PTR [%ESP]
        add %ESP, 4
        ret

Now we produce this:

int:
        mov %EAX, DWORD PTR [%ESP + 4]
        fild DWORD PTR [%EAX]
        ret

... which is nicer.

llvm-svn: 12846

test/Regression/CodeGen/X86/fp_load_fold.llx

llvm-svn: 12844

llvm-svn: 12842

for mul and div.

Instead of generating this:

test_divr:
        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [.CPItest_divr_0]
        fdivrp %ST(1)
        ret

We now generate this:

test_divr:
        fld QWORD PTR [%ESP + 4]
        fdivr QWORD PTR [.CPItest_divr_0]
        ret

This code desperately needs refactoring, which will come in the next
patch.

llvm-svn: 12841

instructions use.  This doesn't change any functionality except that long
constant expressions of these operations will now magically start working.

llvm-svn: 12840

        fld QWORD PTR [%ESP + 4]
        fadd QWORD PTR [.CPItest_add_0]

instead of:

        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [.CPItest_add_0]
        faddp %ST(1)

I also intend to do this for mul & div, but it appears that I have to
refactor a bit of code before I can do so.

This is tested by: test/Regression/CodeGen/X86/fp_constant_op.llx

llvm-svn: 12839

llvm-svn: 12838

llvm-svn: 12836

  1. If an incoming argument is dead, don't load it from the stack
  2. Do not code gen noop copies at all (ie, cast int -> uint), not even to
     a move.  This should reduce register pressure for allocators that are
     unable to coallesce away these copies in some cases.

llvm-svn: 12835

llvm-svn: 12815

is listed first and the address is listed second.

llvm-svn: 12795

llvm-svn: 12787

InstSelectSimple.cpp:
  Change the checks for proper I/O port address size into an exit() instead
  of an assertion.  Assertions aren't used in Release builds, and handling
  this error should be graceful (not that this counts as graceful, but it's
  more graceful).

  Modified the generation of the IN/OUT instructions to have 0 arguments.
X86InstrInfo.td:
  Added the OpSize attribute to the 16 bit IN and OUT instructions.

llvm-svn: 12786

I/O port instructions on x86.  The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output.  This required adjustment to some
methods so that a leading comma would or would not be printed.

llvm-svn: 12782

llvm-svn: 12766

llvm-svn: 12765

llvm-svn: 12764

llvm-svn: 12760

llvm-svn: 12759

llvm-svn: 12758

function prologues, and fix an off-by-one in visitCallInst that was
putting call args into the wrong registers.

llvm-svn: 12757

trying to get incoming args off the stack, instead of the %i0...%i6 regs,
which is wrong.

llvm-svn: 12756

have no good way of handling this until the code generator is improved.
We should probably just emit V9 instructions in the meantime.

llvm-svn: 12745

llvm-svn: 12744

llvm-svn: 12743

llvm-svn: 12742

llvm-svn: 12741

llvm-svn: 12740

llvm-svn: 12739

llvm-svn: 12737

llvm-svn: 12736

llvm-svn: 12735

llvm-svn: 12734

llvm-svn: 12733

Preliminary support for division. It's gross because you have to initialize
the "Y" register, which is the top 32 bits of the thing you're dividing.

llvm-svn: 12732

llvm-svn: 12731

llvm-svn: 12730

Fill in addPassesToJITCompile method.

llvm-svn: 12729