llvm-svn: 55878

llvm-svn: 55876

def : Pat<(i8 (trunc GR32:$src)),
          (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>

llvm-svn: 55875

Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.

llvm-svn: 55679

Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.

llvm-svn: 55623

llvm-svn: 55545

llvm-svn: 55512

llvm-svn: 55504

Add support for fast-isel of opcodes that require use of extract_subreg.  Because of how extract_subreg is treated, it requires special case handling.

llvm-svn: 55480

llvm-svn: 55418

llvm-svn: 55401

llvm-svn: 55394

put each major step in a separate function. This makes the high
level sequence of events easier to follow.

llvm-svn: 55385

- fix to please VS: add a return after an assert.

llvm-svn: 55380

have a return type that differs from the operand types.

llvm-svn: 55376

llvm-svn: 55363

in the example attached to PR2590, but is a problem in general.

llvm-svn: 55361

llvm-svn: 55360

orders, part of PR2590

llvm-svn: 55359

Throw the switch to allow FastISel to emit instructions whose return types different from their inputs.  Next step: adding lowering pattens in FastISel that actually use these newly available opcodes.

llvm-svn: 55349

Enhance TableGen to emit code for FastISel of opcodes with variadic return types without slowing down opcodes that are not variadic.  No such opcodes are currently generated, but in theory it should be a matter of just hitting the switch.

llvm-svn: 55347

Add a RetVT parameter to emitted FastISel methods, so that we will be able to pass the desired return
type down.  This is not currently used.

llvm-svn: 55345

Deepen the map structure tablegen uses to compute FastISel patterns, in preparation for having patterns
with return types that differ from their input types.  This is not yet used.

llvm-svn: 55344

bitcast of constants in fast isel.

llvm-svn: 55325

process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.

Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.

To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.

llvm-svn: 55219

llvm-svn: 55157

and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.

llvm-svn: 55156

llvm-svn: 55099

llvm-svn: 55096

llvm-svn: 55093

llvm-svn: 55080

namespace out of the isel emitters and into common code.

llvm-svn: 55079

class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.

llvm-svn: 55076

llvm-svn: 55034

register class.

llvm-svn: 55008

helper function.

llvm-svn: 55007

llvm-svn: 55004

llvm-svn: 55003

FastISel doesn't support yet.

llvm-svn: 55002

llvm-svn: 54998