to the MachineFunction.

llvm-svn: 77753

llvm-svn: 77752

in SelectionDAGLowering::visitTargetIntrinsic.

This removes a bit of special-case code for vector types.  After staring
at it for a while, I managed to convince myself that it is not necessary.
The only case where TLI.getValueType() differs from MVT::getMVT is for iPTR,
so this code could potentially make a difference for a vector of pointers.
But, it looks like that is not supported.  Calling TLI.getValueType() on
a vector of pointers leads to the following sequence of calls:

TargetLowering::getValueType
MVT::getMVT
MVT::getVectorVT(iPTR, num elements)
MVT::getExtendedVectorVT
MVT::getTypeForMVT for iPTR
assertion fails "Type is not extended!"

So, unless I'm really missing something, this bit of code is irrelevant to
the current version of LLVM, which is consistent with the fact that I don't
see this code in other similar places.

llvm-svn: 77747

need the PreferredEHDataFormat hook, but I have yet-more refactoring to
do before I can zap it.

llvm-svn: 77742

have no functionality change.

llvm-svn: 77741

Simplify operand padding by keying off tabs in the asm stream.  If
padding is disabled, tabs get replaced by spaces except in the case of
the first operand, where the tab is output to line up the operands after
the mnemonics.

Add some better comments and eliminate redundant code.

Fix some testcases to not assume tabs.

llvm-svn: 77740

thing is #if0'd out anyway.  Just simplify the code by reducing the interface.
Not deleting this is essential for Bill's continuing happiness.

llvm-svn: 77736

indicate that it is a predicate, not an emitter.  This eliminates TAI
dependencies on Mangler and GlobalValue.

llvm-svn: 77726

metadata related, which I'm waiting on to avoid conflicting with Devang.

llvm-svn: 77721

llvm-svn: 77709

MCSection subclasses yet, but this is a step in the right direction.

llvm-svn: 77708

llvm-svn: 77704

shouldn't do AU.setPreservesCFG(), because even though CodeGen passes
don't modify the LLVM IR CFG, they may modify the MachineFunction CFG,
and passes like MachineLoop are registered with isCFGOnly set to true.

llvm-svn: 77691

initialize method, which can be called when an MCContext is available.

llvm-svn: 77687

llvm-svn: 77685

failures when building assorted projects with clang.

--- Reverse-merging r77654 into '.':
U    include/llvm/CodeGen/Passes.h
U    include/llvm/CodeGen/MachineFunctionPass.h
U    include/llvm/CodeGen/MachineFunction.h
U    include/llvm/CodeGen/LazyLiveness.h
U    include/llvm/CodeGen/SelectionDAGISel.h
D    include/llvm/CodeGen/MachineFunctionAnalysis.h
U    include/llvm/Function.h
U    lib/Target/CellSPU/SPUISelDAGToDAG.cpp
U    lib/Target/PowerPC/PPCISelDAGToDAG.cpp
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/MachineVerifier.cpp
U    lib/CodeGen/MachineFunction.cpp
U    lib/CodeGen/PrologEpilogInserter.cpp
U    lib/CodeGen/MachineLoopInfo.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
D    lib/CodeGen/MachineFunctionAnalysis.cpp
D    lib/CodeGen/MachineFunctionPass.cpp
U    lib/CodeGen/LiveVariables.cpp

llvm-svn: 77661

mechanism. To support this, make MachineFunctionPass a little more
complete.

llvm-svn: 77654

llvm-svn: 77649

llvm-svn: 77640

llvm-svn: 77635

Start using DebugInfoFinder.

llvm-svn: 77621

Allow targets to define libcall names for mem(cpy,set,move) intrinsics, rather than hardcoding them in DAG lowering.

llvm-svn: 77586

Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. 

When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.

This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.

Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.

llvm-svn: 77582

llvm-svn: 77516

now that TargetOperandInfo does the heavy lifting.

llvm-svn: 77508

llvm-svn: 77505

   and convert code to using it, instead of having lots of things
   poke the isLookupPtrRegClass() method directly.

2. Make PointerLikeRegClass contain a 'kind' int, and store it in
   the existing regclass field of TargetOperandInfo when the
   isLookupPtrRegClass() predicate is set.  Make getRegClass pass
   this into TargetRegisterInfo::getPointerRegClass(), allowing
   targets to have multiple ptr_rc things.

llvm-svn: 77504

llvm-svn: 77495

llvm-svn: 77494

No functionality change.

llvm-svn: 77432

llvm-svn: 77412

  correct. But what are you going to do? I'll fix this in the future.
- Move another large loop into its own method.

llvm-svn: 77408

Does any one else hate the name "const_reverse_iterator" as much as I do?

llvm-svn: 77399

llvm-svn: 77394

llvm-svn: 77393

going to emit.

llvm-svn: 77382

llvm-svn: 77373

llvm-svn: 77369

llvm-svn: 77366

llvm-svn: 77354