and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.

llvm-svn: 108570

llvm-svn: 108567

llvm-svn: 108566

llvm-svn: 108565

Thumb2ITBlockPass.

llvm-svn: 108564

thus is a much more meaningful name.

llvm-svn: 108563

The isLive() method can read uninitialized memory, but it still gives correct
results.

llvm-svn: 108561

PowerPC.

llvm-svn: 108555

llvm-svn: 108547

llvm-svn: 108545

operands.

Hopefully this fixes the llvm-gcc-powerpc-darwin9 buildbot. It really shouldn't
since missing memoperands should not affect correctness.

llvm-svn: 108540

pass that inserted it.

It is no longer necessary to limit the live ranges of FP registers to a single
basic block.

llvm-svn: 108536

llvm-svn: 108535

FP_REG_KILL instructions are still inserted, but can be disabled by passing
-live-x87 to llc. The X87FPRegKillInserterPass is going to be removed shortly.

CFG edges are partioned into bundles where the x87 stack must be allocated
identically. Code is insertad at the end of each basic block that shuffles the
live FP registers to match the outgoing bundles expectations.

This fix is in preparation for some upcoming register allocator improvements
that may extend the live range of registers beyond a basic block, similar to
LICM. It also provides a nice runtime speedup if you are building with
-mfpmath=387.

llvm-svn: 108529

-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.

llvm-svn: 108465

this fixes rdar://8192860.  Unfortunately it can only be triggered
with llc because llvm-mc matches another (correctly encoded) version
of this, so no testcase.

llvm-svn: 108454

llvm-svn: 108396

llvm-svn: 108387

instructions use different values (e.g., 2-byte or 4-byte alignment).
Also fix ARMInstPrinter to print these alignments as bits instead of bytes.

llvm-svn: 108386

lowering atomics. This will allow those copies to still be coalesced after
TII::isMoveInstr is removed.

llvm-svn: 108385

llvm-svn: 108368

llvm-svn: 108366

patch by Michael Spencer!

llvm-svn: 108342

in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284

llvm-svn: 108339

Patch by Brian Lucas. PR7636.

llvm-svn: 108332

llvm-svn: 108328

address cannot be allocated a register is in 32-bit mode where the first
three arguments are marked inreg. In that case EAX, EDX, and ECX will be
used for argument passing.

This fixes PR7610.

llvm-svn: 108327

llvm-svn: 108324

of the value of the immediate.

llvm-svn: 108323

llvm-svn: 108309

Radar 7373643.

llvm-svn: 108303

constants, since they may not be emited near the other instructions
which get the same line, and this confuses debug info.

llvm-svn: 108302

llvm-svn: 108286

NEON VMOV-immediate instructions.  This simplifies some things.

llvm-svn: 108275

Add the x86 VEX_L form to handle special cases where VEX_L must be set.

llvm-svn: 108274

llvm-svn: 108265

Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.

llvm-svn: 108258

llvm-svn: 108256

llvm-svn: 108254

with this commit the callee moves to the end of
the operand array (from the start) and the call
arguments now start at index 0 (formerly 1)

this ordering is now consistent with InvokeInst

this commit only flips the switch,
functionally it is equivalent to
r101465

I intend to commit several cleanups after a few
days of soak period

llvm-svn: 108240