flag so it can be flagged to a FST.

llvm-svn: 25953

- Use XORP* to implement fneg.

llvm-svn: 25857

* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.

llvm-svn: 25854

llvm-svn: 25831

conversions. SSE does not have instructions to handle these tasks.

llvm-svn: 25817

Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.

llvm-svn: 25803

llvm-svn: 25798

the same functionality.  This addresses another piece of bug 680.  Next,
on to fixing Alpha VAARG, which I broke last time.

llvm-svn: 25696

llvm-svn: 25679

Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.

llvm-svn: 25606

llvm-svn: 25257

llvm-svn: 25226

llvm-svn: 25190

llvm-svn: 25158

* FP cmp, setcc, etc.

llvm-svn: 25117

llvm-svn: 25103

llvm-svn: 24990

* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.

llvm-svn: 24921

bytes to pop off stack.
* Added support for X86 SETCC.

llvm-svn: 24917

  for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
  value (or store / fld / copy to ST(0) for floating point value). This
  eliminate the need to write C++ code to handle RET with variable number
  of operands.

llvm-svn: 24888

llvm-svn: 24877

llvm-svn: 24870

llvm-svn: 24754

llvm-svn: 24430

contributed by Evan Cheng.

llvm-svn: 24358