llvm-svn: 27612

llvm-svn: 27603

__builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu.

llvm-svn: 27599

later.

llvm-svn: 27591

llvm-svn: 27590

llvm-svn: 27587

llvm-svn: 27575

llvm-svn: 27569

llvm-svn: 27567

llvm-svn: 27565

llvm-svn: 27564

llvm-svn: 27563

llvm-svn: 27562

llvm-svn: 27556

llvm-svn: 27555

llvm-svn: 27554

letting the code generator handle them directly.

llvm-svn: 27539

llvm-svn: 27506

llvm-svn: 27501

llvm-svn: 27497

llvm-svn: 27496

entry point of a function.

llvm-svn: 27494

llvm-svn: 27491

Also MOVPDI2DIrr.

llvm-svn: 27476

- Normalize shuffle nodes so result vector lower half elements come from the
  first vector, the rest come from the second vector. (Except for the
  exceptions :-).
- Other minor fixes.

llvm-svn: 27474

llvm-svn: 27473

llvm-svn: 27446

llvm-svn: 27445

llvm-svn: 27444

vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>

This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.

It would match a {p}unpckl on x86.

llvm-svn: 27437

llvm-svn: 27434

llvm-svn: 27433

llvm-svn: 27427

llvm-svn: 27412

llvm-svn: 27410

llvm-svn: 27405

llvm-svn: 27393

llvm-svn: 27388

llvm-svn: 27384

Use movhpd to: store upper f64 extracted from v2f64.

llvm-svn: 27382