Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.

llvm-svn: 44960

llvm-svn: 44045

adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...

llvm-svn: 44037

llvm-svn: 41863

llvm-svn: 40132

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

llvm-svn: 31434

llvm-svn: 30945

llvm-svn: 30909

llvm-svn: 30891

llvm-svn: 30844

llvm-svn: 30039

llvm-svn: 30038

llvm-svn: 29603

llvm-svn: 28182

instructions are expensive.

llvm-svn: 26298

and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255

intrinsics.

Autogen frameindex matcher

llvm-svn: 26107

llvm-svn: 26106

llvm-svn: 26080

llvm-svn: 25985

llvm-svn: 25906

llvm-svn: 25905

llvm-svn: 25842

an operand that contains the condcode), making things significantly simpler.

llvm-svn: 25840

a CC as an operand.  Much smaller, much happier.

llvm-svn: 25839

llvm-svn: 25838

llvm-svn: 25837

llvm-svn: 25834

SPARC condition codes, not in terms of the DAG condcodes.  This allows us to
write nice clean patterns for cmovs/branches.

llvm-svn: 25815

uint %test(uint %X) {
        %Y = call uint %llvm.ctpop.i32(uint %X)
        ret uint %Y
}

to:

test:
        save -96, %o6, %o6
        sll %i0, 0, %l0
        popc %l0, %i0
        restore %g0, %g0, %g0
        retl
        nop

instead of to 40 logical ops.  Note the shift-by-zero that clears the top
part of the 64-bit V9 register.

Testcase here: CodeGen/SparcV8/ctpop.ll

llvm-svn: 25814

llvm-svn: 25810

patterns.  This allows emission of this code:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        move %icc, %i0, %i2
        or %g0, %i2, %i0
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        be .LBBt1_2     !
        nop
.LBBt1_1:       !
        or %g0, %i2, %i0
.LBBt1_2:       !
        restore %g0, %g0, %g0
        retl
        nop

for this:

int %t1(int %a, int %b, int %c) {
        %tmp.2 = seteq int %a, %b
        %tmp3 = select bool %tmp.2, int %a, int %c
        ret int %tmp3
}

llvm-svn: 25809

llvm-svn: 25716

llvm-svn: 25674

Compile this:

%_2E_str_8 = external global [75 x sbyte]
implementation   ; Functions:
declare int %printf(sbyte*, ...)
void %test()
        %tmp.101 = call int (sbyte*, ...)* %printf( sbyte* getelementptr ([75 x sbyte]* %_2E_str_8, int 0, int 0) )             ; <int> [#uses=0]
        unreachable
}

to this:

main_endif_2E_8:
        save -96, %o6, %o6
        sethi %hi(_2E_str_8), %l0
        add %l0, %lo(_2E_str_8), %o0
        call printf
        nop

instead of this:

main_endif_2E_8:
        save -96, %o6, %o6
        sethi %hi(_2E_str_8), %l0
        or %g0, %lo(_2E_str_8), %l1   ;; extra instruction
        add %l1, %l0, %o0
        call printf
        nop

llvm-svn: 25335

llvm-svn: 25249

pattern for SUBCCrr, and makes it trivial to add support for SUBCCri, eliminating
an instruction in the common "setcc X, imm" case.

llvm-svn: 25212

llvm-svn: 25210

This implements Regression/CodeGen/SparcV8/xnor.ll

llvm-svn: 25209