- Consolidate instruction formats.
- Other clean up.

llvm-svn: 58808

llvm-svn: 58800

llvm-svn: 58793

llvm-svn: 58790

llvm-svn: 58789

llvm-svn: 58780

Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.

llvm-svn: 58764

priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.

The impact on most targets is that AddToISelQueue calls can be simply removed.

In the x86 target, there are two additional notable changes.

The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.

Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.

llvm-svn: 58748

llvm-svn: 58725

llvm-svn: 58714

llvm-svn: 58708

llvm-svn: 58707

For some targets, it's not possible to place GVs in the same memory buffer as the MachineCodeEmitter allocated memory. Code and data has different read / write / execution privilege requirements.

This is a short term workaround. The current solution is for the JIT memory manager to manage code and data memory separately.

llvm-svn: 58688

llvm-svn: 58683

llvm-svn: 58671

llvm-svn: 58644

llvm-svn: 58643

Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.

llvm-svn: 58626

adding a TargetMachine member to the base TargetAsmInfo class instead.

llvm-svn: 58624

llvm-svn: 58533

llvm-svn: 58532

llvm-svn: 58529

llvm-svn: 58527

llvm-svn: 58526

llvm-svn: 58474

llvm-svn: 58433

llvm-svn: 58409

llvm-svn: 58408

Since the ARM constant pool handling supercedes the standard LLVM constant
pool entirely, the JIT emitter does not allocate space for the constants,
nor initialize the memory. The constant pool is considered part of the 
instruction stream.

Likewise, when resolving relocations into the constant pool, a hook into
the target back end is used to resolve from the constant ID# to the
address where the constant is stored.

For now, the support in the ARM emitter is limited to 32-bit integer. Future
patches will expand this to the full range of constants necessary.

llvm-svn: 58338

Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag.  Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like.  This really helps when debugging instruction selection.

llvm-svn: 58278

llvm-svn: 58133

llvm-svn: 58006

names of LLVMCore and ARMCodeGen.

llvm-svn: 57943

llvm-svn: 57911

is re-written by the callback to branch directly to the compiled code
in future invocations.

Added back in range-based memory permission functions for the updating of
the stub on Darwin.

llvm-svn: 57846

llvm-svn: 57622

llvm-svn: 57526

llvm-svn: 57524

instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.

llvm-svn: 57521

parameters instead of raw Constants.  This prevents the constants from
being selected by the isel pass, fixing PR2735.

llvm-svn: 57385