rdar://10348844

llvm-svn: 143110

rdar://10348584

llvm-svn: 143108

llvm-svn: 143086

llvm-svn: 143080

up.  Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle.  This creates many more 
opportunities for target specific fast-isel.

llvm-svn: 143079

place.  No functional change intended.

llvm-svn: 143078

llvm-svn: 143076

SelectBranch.  No functional change intended.

llvm-svn: 143072

We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.

More of rdar://10348687

llvm-svn: 143068

Patch by Sanjoy Das.

llvm-svn: 143064

Partial fix for rdar://10348687.

llvm-svn: 143063

MORESTACK_RET_RESTORE_R10; which are lowered to a RET and a RET
followed by a MOV respectively.  Having a fake instruction prevents
the verifier from seeing a MachineBasicBlock end with a
non-terminator (MOV).  It also prevents the rather eccentric case of a
MachineBasicBlock ending with RET but having successors nevertheless.

Patch by Sanjoy Das.

llvm-svn: 143062

llvm-svn: 143055

llvm-svn: 143034

Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance.

llvm-svn: 143023

Use a worklist to prevent the iterator from becoming invalidated because of the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot.

llvm-svn: 143018

on Darwin platforms where -Os means optimize for size without hurting
performance.

llvm-svn: 143002

The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned

Patch by Petar Jovanovic.

llvm-svn: 142930

Four entry register lists.

llvm-svn: 142882

llvm-svn: 142880

llvm-svn: 142878

llvm-svn: 142877

Three entry register list variation.

llvm-svn: 142876

llvm-svn: 142871

llvm-svn: 142867

One and two length register list variants.

llvm-svn: 142861

Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.

llvm-svn: 142853

llvm-svn: 142841

Fix a NEON disassembly case that was broken in the recent refactorings.  As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.

llvm-svn: 142817

use of Sched::ILP instead, as Sched::Latency is going away.

llvm-svn: 142813

as the Latency scheduler is going away.

llvm-svn: 142811

PR11220

llvm-svn: 142801

llvm-svn: 142779

llvm-svn: 142741

llvm-svn: 142738

llvm-svn: 142737

llvm-svn: 142726

SHL inserts zeros from the right, thus even when the original
sign_extend_inreg value was of 1-bit, we need to sra.

llvm-svn: 142724

that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2

llvm-svn: 142706

llvm-svn: 142704