llvm-svn: 15011

llvm-svn: 14991

is sorted.  This is not the case currently, which is causing no end of
problems.

llvm-svn: 14990

llvm-svn: 14626

llvm-svn: 14590

existing llvm::Interval class.

Patch contributed by Vladimir Prus!
http://mail.cs.uiuc.edu/pipermail/llvmbugs/2004-June/000710.html

llvm-svn: 14281

llvm-svn: 13910

spills. This allows for more flexibility when allocating registers for
spill code.

llvm-svn: 13907

llvm-svn: 13417

workaround, use the C HUGE_VAL macro instead.

llvm-svn: 13377

unhandled + handled. So unhandled is now including all fixed intervals
and fixed intervals never changes when processing a function.

llvm-svn: 12462

Add a spiller option to llc. A simple spiller will come soon. When we get CFG in the machine code represenation a global spiller will also be possible. Also document the linear scan register allocator but mark it as experimental for now.

llvm-svn: 12062

llvm-svn: 12058

llvm-svn: 11898

llvm-svn: 11841

llvm-svn: 11830

allocator.

The implementation is completely rewritten and now employs several
optimizations not exercised before. For example for 164.gzip we have
997 loads and 699 stores vs the 1221 loads and 880 stores we have
before.

llvm-svn: 11798

llvm-svn: 11781

251 (providing a generic machine code rewriter/spiller).

llvm-svn: 11780

llvm-svn: 11759

llvm-svn: 11755

Improved PhysRegTracker interface. RegAlloc lazily allocates the register tracker using a std::auto_ptr

llvm-svn: 11738

Fix comments in PhysRegTracker and rename isPhysRegAvail to isRegAvail to be consistent with the other two

llvm-svn: 11723

llvm-svn: 11720

llvm-svn: 11719

llvm-svn: 11704

llvm-svn: 11659

llvm-svn: 11655

1. LiveIntervals now implement a 4 slot per instruction model. Load,
   Use, Def and a Store slot. This is required in order to correctly
   represent caller saved register clobbering on function calls,
   register reuse in the same instruction (def resues last use) and
   also spill code added later by the allocator. The previous
   representation (2 slots per instruction) was insufficient and as a
   result was causing subtle bugs.

2. Fixes in spill code generation. This was the major cause of
   failures in the test suite.

3. Linear scan now has core support for folding memory operands. This
   is untested and not enabled (the live interval update function does
   not attempt to fold loads/stores in instructions).

4. Lots of improvements in the debugging output of both live intervals
   and linear scan. Give it a try... it is beautiful :-)

In summary the above fixes all the issues with the recent reserved
register elimination changes and get the allocator very close to the
next big step: folding memory operands.

llvm-svn: 11654

llvm-svn: 11629

llvm-svn: 11619

llvm-svn: 11609

llvm-svn: 11476

std::numeric_limits<float>::max() for weighting preallocated
intervals.

llvm-svn: 11427

llvm-svn: 11393

ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.

llvm-svn: 11340

llvm-svn: 11283

llvm-svn: 11151

of the virtual register to certain functions.

llvm-svn: 11143

operand of the instruction and thus simplify the register allocation.

llvm-svn: 11124