loads instead of 1 x i64 loads.  This doesn't change any functionality yet.

llvm-svn: 43068

llvm-svn: 43066

llvm-svn: 43033

doesn't fit into 16 bits.

llvm-svn: 43032

was stored to the acutal stack slot before the parameters were
lowered to their stack slot. This could cause arguments to be
overwritten by the return address if the called function had less
parameters than the caller function. The update should remove the
last failing test case of llc-beta: SPASS.

llvm-svn: 43027

unconditionally creating an i64 bitcast.  With the future legalizer
design, operation legalization can't introduce new nodes with illegal
types.

This fixes the rest of olden on ppc32.

llvm-svn: 43005

llvm-svn: 43004

llvm-svn: 42972

llvm-svn: 42962

llvm-svn: 42960

a problem when asserts are on).  From vecLib.

llvm-svn: 42959

trampolines, rather than with nested functions themselves.

llvm-svn: 42955

register used by the unfolded instructions. User can also specify whether to
unfold the load, the store, or both.

llvm-svn: 42946

llvm-svn: 42935

for fastcc from X86CallingConv.td.  This means that nested functions
are not supported for calling convention 'fastcc'.

llvm-svn: 42934

longer be created for fastcc functions.

llvm-svn: 42925

llvm-svn: 42922

function symbol name instead of a codegen-assigned function
number.

Thanks Evan! :-)

llvm-svn: 42908

llvm-svn: 42905

llvm-svn: 42904

llvm-svn: 42895

llvm-svn: 42894

llvm-svn: 42881

llvm-svn: 42874

enabled by passing -tailcallopt to llc.  The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
  elf/pic enabled + callee is in module + callee has
  visibility protected or hidden

llvm-svn: 42870

illegal.  Thanks to gabor for pointing this out!

llvm-svn: 42832

Surprisingly complicated.
Adds getTargetNode for 2 outputs, no inputs (missing).

llvm-svn: 42822

llvm-svn: 42787

llvm-svn: 42786

llvm-svn: 42785

llvm-svn: 42783

llvm-svn: 42780

- Added a function to hold the stack location 
  where GP must be stored during LowerCALL
- AsmPrinter now emits directives based on
  relocation type
- PIC_ set to default relocation type (same as GCC)

llvm-svn: 42779

- Modified instruction format to handle pseudo instructions
- Added LoadAddr SDNode to load symbols.

llvm-svn: 42778

llvm-svn: 42774

use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.

llvm-svn: 42762

llvm-svn: 42761

target-indepenent lowering, don't use them on PowerPC.

llvm-svn: 42755

llvm-svn: 42751

llvm-svn: 42739