gross hack (having the asmmatcher handle the alias).

llvm-svn: 115685

the right places.  X86Instr64bit.td now dies, long live x86-64!

llvm-svn: 115669

llvm-svn: 115663

llvm-svn: 115660

llvm-svn: 115632

llvm-svn: 115631

llvm-svn: 115627

llvm-svn: 115608

llvm-svn: 115607

llvm-svn: 115606

llvm-svn: 115605

bswap32 doesn't read eflags.

llvm-svn: 115604

pseudo instructions.

Move POPCNT to InstrSSE since they are SSE4 instructions.

llvm-svn: 115603

with the 32-bit stuff.

llvm-svn: 115602

llvm-svn: 115601

llvm-svn: 115600

llvm-svn: 115599

llvm-svn: 115598

llvm-svn: 115597

control flow stuff out to X86InstrControl.td.  Move
some compiler pseudo instructions and Pat<> patterns
out to X86InstrCompiler.td

llvm-svn: 115596

llvm-svn: 115591

it in with the SSSE3 instructions.

Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!

llvm-svn: 115552

Patch by Cameron!

llvm-svn: 115480

Based on the patch by Cameron Esfahani!

llvm-svn: 115479

llvm-svn: 115477

the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended.  This fixes PR8288

llvm-svn: 115473

so and also change X86 for consistency.

Investigating if this can be improved a bit.

llvm-svn: 115469

the right file.  The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.

llvm-svn: 115468

llvm-svn: 115467

else in X86), and add support for pavgusb.  This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.

If someone else is interested in banging out the rest of the 3DNow! 
instructions, it should be quite easy now.

llvm-svn: 115466

llvm-svn: 115429

backing int_x86_ssse3_pshuf_w got removed.  This caused PR8280.

llvm-svn: 115422

been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.

llvm-svn: 115360

llvm-svn: 115311

The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.

Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics. 

MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces.  Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.

The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.

llvm-svn: 115243

use MC instructions in the printInstruction() method via the tablegen flag
for it rather than a #define prior to including the autogenerated bits.

llvm-svn: 115238

llvm-svn: 115168

llvm-svn: 115156

llvm-svn: 115154

for the dwarf .loc support to emit dwarf line number tables.

llvm-svn: 115153