llvm-svn: 64361

Remove a bogus assertion. It's possible a live-in available value is used by a previous instruction.

llvm-svn: 64339

unless they actually have data successors, and likewise for nodes
with no data successors unless they actually have data precessors.

llvm-svn: 64327

It was transforming (x&y)==y to (x&y)!=0 in the case where
y is variable and known to have at most one bit set (e.g. z&1).
This is not correct; the expressions are not equivalent when y==0.
I believe this patch salvages what can be salvaged, including
all the cases in bt.ll.  Dan, please review.
Fixes gcc.c-torture/execute/20040709-[12].c

llvm-svn: 64314

Implement PR3495: local spiller optimization. The local spiller can now keep availability information over BB boundaries. It visits BB's in depth first order. After visiting a BB if it find a successor which has a single predecessor it visits the successor next without clearing the availability information. This allows the successor to omit reloads or change them into copies.

llvm-svn: 64298

llvm-svn: 64240

Fix PR3457: Ignore control successors when looking for closest scheduled successor. A control successor doesn't read result(s) produced by the scheduling unit being evaluated.

llvm-svn: 64210

llvm-svn: 64186

llvm-svn: 64163

llvm-svn: 64126

Fix PR3486. Fix a bug in code that manually patch physical register live interval after its sub-register is coalesced with a virtual register.

llvm-svn: 64082

llvm-svn: 64073

llvm-svn: 64062

llvm-svn: 63999

llvm-svn: 63906

isAsCheapAsMove instructions can have register src operands. Check if they are really re-materializable.
This fixes sse.expandfft and sse.stepfft.

llvm-svn: 63890

llvm-svn: 63855

sure to print the value properly sext'd to the right pointer size.
This fixes PR3481.

llvm-svn: 63843

llvm-svn: 63774

of undefs and incorrectly determining if we have punpckldq.

llvm-svn: 63702

in any old order.  Since analyzing a node analyzes its
operands also, this can mean that when we pop a node
off the list of nodes to be analyzed, it may already
have been analyzed.

llvm-svn: 63632

With the new world order, it can handle cases where the first
store into the alloca is an element of the vector, instead of
requiring the first analyzed store to have the vector type 
itself.  This allows us to un-xfail 
test/CodeGen/X86/vec_ins_extract.ll.

llvm-svn: 63590

default to -march=x86-64 on 64-bit hosts.

llvm-svn: 63579

llvm-svn: 63572

llvm-svn: 63561

llvm-svn: 63533

Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow.

llvm-svn: 63505

--This line, and those below, will be ignaored--

A    test/CodeGen/X86/nosse-error1.ll
A    test/CodeGen/X86/nosse-error2.ll

llvm-svn: 63496

var-args, and don't allow FP return values

llvm-svn: 63495

crashes or wrong code with codegen of large integers:
eliminate the legacy getIntegerVTBitMask and
getIntegerVTSignBit methods, which returned their
value as a uint64_t, so couldn't handle huge types.

llvm-svn: 63494

returned by getShiftAmountTy may be too small
to hold shift values (it is an i8 on x86-32).
Before and during type legalization, use a large
but legal type for shift amounts: getPointerTy;
afterwards use getShiftAmountTy, fixing up any
shift amounts with a big type during operation
legalization.  Thanks to Dan for writing the
original patch (which I shamelessly pillaged).

llvm-svn: 63482

when A==B, -0.0 != +0.0.

llvm-svn: 63474

XFAIL this test.  It only worked before because of a bug in the spill point selection code.  Not deleting because 
it should be possible to enhance the selection code to handle this in the future.

llvm-svn: 63340

Local register allocator shouldn't assume only the entry and landing pad basic blocks have live-ins.

llvm-svn: 63323

the element indices may be equal if either one is not a
constant.

llvm-svn: 63311

llvm-svn: 63267

dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.

llvm-svn: 63266

llvm-svn: 63252

llvm-svn: 63247

The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement.

llvm-svn: 63195