rdar://problem/8893967: JM/lencod miscompile at -arch armv7 -mthumb -O3

Added ResurrectKill to remove kill flags after we decide to reused a
physical register. And (hopefully) ensure that we call it in all the
right places.

Sorry, I'm not checking in a unit test given that it's a miscompile I
can't reproduce easily with a toy example. Failures in the rewriter
depend on a series of heuristic decisions maked during one of the many
upstream phases in codegen. This case would require coercing regalloc
to generate a couple of rematerialzations in a way that causes the
scavenger to reuse the same register at just the wrong point.

The general way to test this is to implement kill flags
verification. Then we could have a simple, robust compile-only unit
test. That would be worth doing if the whole pass was not about to
disappear. At this point we focus verification work on the next
generation of regalloc.

llvm-svn: 124442

Clang: separate the access-control diagnostics from other diagnostics that do not have SFINAE behavior.

llvm-svn: 124440

llvm-svn: 124426

llvm-svn: 124406

llvm-svn: 124404

llvm-config --cflags --cxxflags --cppflags

We shouldn't impose those flags on people who use llvm-config for
building their own projects.

llvm-svn: 124399

llvm-svn: 124397

Take 2. This includes fix for dragonegg crash.

llvm-svn: 124380

Add support for specifying register name in cfi-register/offset/def
as well as register number.

llvm-svn: 124379

Create override of this method in X86/ARM/MBlaze.

llvm-svn: 124378

llvm-svn: 124375

llvm-svn: 124370

that relationships like "i8* null" is equivalent to "i32* null".

llvm-svn: 124368

Don't infinitely recurse!  Patch by Marius Wachtler!

llvm-svn: 124366

Linear scan regalloc is currently assuming that any register aliased with
a member of a regclass must also be in at least one regclass.  That is not
always true.  For example, for X86, RIP is in a regclass but IP is not.
If you're unlucky, this can cause a crash by invalidating the iterator.

llvm-svn: 124365

llvm-svn: 124358

if we can store a value. Also, the exclusion is or, not and.

Fixes rdar://8920247.

llvm-svn: 124357

CALL64 marks %xmm* as dead.

llvm-svn: 124354

llvm-svn: 124350

llvm-svn: 124346

llvm-svn: 124339

llvm-svn: 124331

llvm-svn: 124330

Patch by Bill Wendling.

llvm-svn: 124328

llvm-svn: 124327

llvm-svn: 124324

llvm-svn: 124323

llvm-svn: 124320

parser. The parser will always give us a binary representation of the floating
point number.

llvm-svn: 124318

When an operand class is defined with MIOperandInfo set to a list of
suboperands, the AsmMatcher has so far required that operand to also define
a custom ParserMatchClass, and InstAlias patterns have not been able to
set the individual suboperands separately.  This patch removes both of those
restrictions.  If a "compound" operand does not override the default
ParserMatchClass, then the AsmMatcher will now parse its suboperands
separately.  If an InstAlias operand has the same class as the corresponding
compound operand, then it will be handled as before; but if that check fails,
TableGen will now try to match up a sequence of InstAlias operands with the
corresponding suboperands.

llvm-svn: 124314

llvm-svn: 124312

- Print a summary of breakpoints in the beginning.

llvm-svn: 124308

[AVX] Add INSERT_SUBVECTOR and support it on x86.  This provides a
default implementation for x86, going through the stack in a similr
fashion to how the codegen implements BUILD_VECTOR.  Eventually this
will get matched to VINSERTF128 if AVX is available.

llvm-svn: 124307

llvm-svn: 124302

llvm-svn: 124301

llvm-svn: 124300

[AVX] Support EXTRACT_SUBVECTOR on x86.  This provides a default
implementation of EXTRACT_SUBVECTOR for x86, going through the stack
in a similr fashion to how the codegen implements BUILD_VECTOR.
Eventually this will get matched to VEXTRACTF128 if AVX is available.

llvm-svn: 124292

llvm-svn: 124289

llvm-svn: 124288

operand being factorized (and erased) could occur several times in Ops,
resulting in freed memory being used when the next occurrence in Ops was
analyzed.

llvm-svn: 124287