Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.

llvm-svn: 37199

Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.

llvm-svn: 37118

llvm-svn: 37103

llvm-svn: 37066

llvm-svn: 36948

llvm-svn: 36519

llvm-svn: 36518

llvm-svn: 36506

llvm-svn: 36222

flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).

llvm-svn: 35573

llvm-svn: 35381

    mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218

Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool.

llvm-svn: 35207

llvm-svn: 35163

rematerializable. Only used for constant generation for now.

llvm-svn: 35162

llvm-svn: 35161

llvm-svn: 33832

        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

- In thumb mode, it's not possible to use .set generate a pc relative stub
  address. The stub is ARM code which is in a different section from the thumb
  code. Load the value from a constpool instead.
- Some asm printing clean up.

llvm-svn: 33664

llvm-svn: 33537

llvm-svn: 33368

llvm-svn: 33353

patch by Lauro
bug fixed by me

llvm-svn: 32795

llvm-svn: 32762

bug noticed by Lauro

llvm-svn: 32761

arm.

llvm-svn: 32760

llvm-svn: 32484

llvm-svn: 32459

llvm-svn: 32454

llvm-svn: 32364

remove lea_addri and the now unused memri addressing mode

llvm-svn: 31592

TODO: fix lea_addri

llvm-svn: 31552

llvm-svn: 31435

llvm-svn: 31348

llvm-svn: 31160

llvm-svn: 31138

llvm-svn: 31052

llvm-svn: 31049

llvm-svn: 31047

llvm-svn: 31037

llvm-svn: 31036