when there are no uses. This fixes a dangling-pointer bug, where pointers to
deleted instructions were not removed from kills lists. More info here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2007-July/009749.html

llvm-svn: 40131

This hopefully fixes a miscompilation of TargetData.cpp when self hosting.

llvm-svn: 40125

llvm-svn: 40124

llvm-svn: 40123

llvm-svn: 40109

llvm-svn: 40102

pacifies g++-4.2.

llvm-svn: 40089

llvm-svn: 40085

flag when determining what to do with dependencies.

llvm-svn: 40079

code that cross integer / floating point domains (e.g. generate pxor / pand for
logical ops on floating point value, movdqa to load / store floating point SSE
values). Given that, it's better to use movaps instead of movdqa and movups
instead of movdqu. They have the same latency but the "aps" variants are one
byte shorter.
If the domain crossing problem is a real performance issue, then we will have to
fix it with dynamic programming based isel.

llvm-svn: 40076

llvm-svn: 40074

llvm-svn: 40071

Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG combiner may fold away the (bit_convert (load)).

llvm-svn: 40070

Change the keywords for the zext and sext parameter attributes to be 
zeroext and signext so they don't conflict with the keywords for the
instructions of the same name. This gets around the ambiguity.

llvm-svn: 40069

the type "unsigned" instead of uintptr_t for a 1-bit structure field.

llvm-svn: 40066

llvm-svn: 40064

llvm-svn: 40062

with hopefully correct code that pleases g++-4.2.

llvm-svn: 40051

what it thought it was doing.

llvm-svn: 40044

llvm-svn: 40043

With this, the time to optimize 403.gcc is down to 15.1s.

llvm-svn: 40042

This results in a slight speedup for 403.gcc.

llvm-svn: 40040

llvm-svn: 40039

reduces the time to optimize 403.gcc from 17.6s to 16.4s.

llvm-svn: 40036

second part dominates all the blocks dominated
by original basic block. And first part dominates
second part.

llvm-svn: 40035

llvm-svn: 40034

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

llvm-svn: 40030

llvm-svn: 40028

llvm-svn: 40025

This fixes PR1559.

llvm-svn: 40024

llvm-svn: 40022

Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if previous instruction updates esp, fold it in.

llvm-svn: 40018

end of a BasicBlock and have an alignment parameter.

llvm-svn: 40016

and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.

llvm-svn: 40015

would result in calling realloc() on a null pointer.  Instead, if we encounter
this situation, make a normal call to malloc().

llvm-svn: 40014

alignment is equal to the stack alignment.

llvm-svn: 40004

llvm-svn: 39998

llvm-svn: 39984

llvm-svn: 39979