BUILD_VECTOR and conversions to stack operations.

llvm-svn: 63333

some assertions.

llvm-svn: 63328

llvm-svn: 63325

Local register allocator shouldn't assume only the entry and landing pad basic blocks have live-ins.

llvm-svn: 63323

llvm-svn: 63312

the element indices may be equal if either one is not a
constant.

llvm-svn: 63311

llvm-svn: 63304

change.

llvm-svn: 63301

llvm-svn: 63300

and an iterator invalidation issue.

FreeBench/pifft no longer miscompiles with these fixes!

llvm-svn: 63293

llvm-svn: 63276

vast majority of code size regressions introduced by pre-alloc-splitting.

llvm-svn: 63274

- Modify TableGen to add the DebugLoc when calling getTargetNode.

(The light-weight wrappers are only temporary. The non-DebugLoc version will be
removed once the whole debug info stuff is finished with.)

llvm-svn: 63273

llvm-svn: 63269

llvm-svn: 63267

dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.

llvm-svn: 63266

after the code that sorts the patterns. This doesn't
affect the output, but it makes the code a little easier
to follow.

llvm-svn: 63265

A slight compile time optimization. If the caller knows there isn't a free register getReg() should not call getFreeReg().

llvm-svn: 63263

functions.  Currently omitted:  memcpy, memmove, memset.

llvm-svn: 63259

llvm-svn: 63255

llvm-svn: 63252

llvm-svn: 63247

llvm-svn: 63245

llvm-svn: 63244

accessed via SDNode::getNode.

llvm-svn: 63240

llvm-svn: 63239

classes (those that reasonably have a DebugLoc
associated with them).

llvm-svn: 63236

llvm-svn: 63234

Do not forget to derived type while constructing an array type.

llvm-svn: 63233

after the others.

llvm-svn: 63227

llvm-svn: 63222

llvm-svn: 63217

llvm-svn: 63214

Patch by Piotr Rak!

llvm-svn: 63213

new isOperationLegalOrCustom, which does what isOperationLegal
previously did.

Update a bunch of callers to use isOperationLegalOrCustom
instead of isOperationLegal. In some case it wasn't obvious
which behavior is desired; when in doubt I changed then to
isOperationLegalOrCustom as that preserves their previous
behavior.

This is for the second half of PR3376.

llvm-svn: 63212

llvm-svn: 63199

llvm-svn: 63198

deleting the escape analysis pass.

llvm-svn: 63197

The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement.

llvm-svn: 63195

llvm-svn: 63194