llvm-svn: 17929

llvm-svn: 17927

llvm-svn: 17926

llvm-svn: 17925

Added my own defMap. Only saving values that are not loop invariant. Fixed a couple of assertions that were triggered due to registers not being allocated. These both had to do with PHINodes.

llvm-svn: 17907

llvm-svn: 17902

llvm-svn: 17895

You can't have implicit defs that overlap explicit defs, or implicit
defs that alias one another.

llvm-svn: 17894

llvm-svn: 17870

hold your nose!)

llvm-svn: 17869

already been emitted, we don't have to remember it and deal with it later,
just emit it directly.

llvm-svn: 17868

* Get rid of "emitMaybePCRelativeValue", either we want to emit a PC relative
  value or not: drop the maybe BS.  As it turns out, the only places where
  the bool was a variable coming in, the bool was a dynamic constant.

llvm-svn: 17867

set up.

llvm-svn: 17862

llvm-svn: 17861

llvm-svn: 17851

llvm-svn: 17823

llvm-svn: 17822

llvm-svn: 17750

llvm-svn: 17749

llvm-svn: 17744

llvm-svn: 17733

Exclude bigfib, so that we effectively exclude all C++ benchmarks.
Update to-do list: mention va_start.

llvm-svn: 17732

not zero.

llvm-svn: 17728

llvm-svn: 17725

llvm-svn: 17723

llvm-svn: 17722

llvm-svn: 17721

llvm-svn: 17714

CBackend/2004-11-13-FunctionPointerCast.llx

llvm-svn: 17710

shld is a very high latency operation. Instead of emitting it for shifts of
two or three, open code the equivalent operation which is faster on athlon
and P4 (by a substantial margin).

For example, instead of compiling this:

long long X2(long long Y) { return Y << 2; }

to:

X3_2:
        movl 4(%esp), %eax
        movl 8(%esp), %edx
        shldl $2, %eax, %edx
        shll $2, %eax
        ret

Compile it to:

X2:
        movl 4(%esp), %eax
        movl 8(%esp), %ecx
        movl %eax, %edx
        shrl $30, %edx
        leal (%edx,%ecx,4), %edx
        shll $2, %eax
        ret

Likewise, for << 3, compile to:

X3:
        movl 4(%esp), %eax
        movl 8(%esp), %ecx
        movl %eax, %edx
        shrl $29, %edx
        leal (%edx,%ecx,8), %edx
        shll $3, %eax
        ret

This matches icc, except that icc open codes the shifts as adds on the P4.

llvm-svn: 17707

llvm-svn: 17706

long long X3_2(long long Y) { return Y+Y; }
int X(int Y) { return Y+Y; }

into:

X3_2:
        movl 4(%esp), %eax
        movl 8(%esp), %edx
        addl %eax, %eax
        adcl %edx, %edx
        ret
X:
        movl 4(%esp), %eax
        addl %eax, %eax
        ret

instead of:

X3_2:
        movl 4(%esp), %eax
        movl 8(%esp), %edx
        shldl $1, %eax, %edx
        shll $1, %eax
        ret

X:
        movl 4(%esp), %eax
        shll $1, %eax
        ret

llvm-svn: 17705

It's stosl (l for long == 32 bit).

llvm-svn: 17658

llvm-svn: 17637

move instructions for the register allocator to coalesce.

llvm-svn: 17608

llvm-svn: 17583

llvm-svn: 17547

llvm-svn: 17544

llvm-svn: 17488

llvm-svn: 17484