llvm-svn: 25985

llvm-svn: 25984

llvm-svn: 25983

llvm-svn: 25980

This patch speeds up 172.mgrid from 31.81s to 11.39s on darwin/ppc.
Many many thanks to Nate for tracking down the root cause of the issue.

llvm-svn: 25979

llvm-svn: 25976

tblgen patch reverted.

llvm-svn: 25971

Select them afterwards if it returns true.

llvm-svn: 25968

case, the double being loaded may not be 8-byte aligned, so we have to use
our standard bit_convert game.

llvm-svn: 25967

llvm-svn: 25966

llvm-svn: 25965

llvm-svn: 25963

llvm-svn: 25962

1. Treat FMOVD as a copy instruction, to help with coallescing in V9 mode
2. When in V9 mode, insert FMOVD instead of FpMOVD instructions, as we don't
   ever rewrite FpMOVD instructions into FMOVS instructions, thus we just end
   up with commented out copies!
This should fix a bunch of failures in V9 mode on sparc.

llvm-svn: 25961

llvm-svn: 25954

flag so it can be flagged to a FST.

llvm-svn: 25953

llvm-svn: 25951

llvm-svn: 25946

llvm-svn: 25945

llvm-svn: 25944

llvm-svn: 25943

llvm-svn: 25942

llvm-svn: 25940

obsolete.  yaay :)

llvm-svn: 25939

instruction when possible.

llvm-svn: 25938

Remove the dead getRegClassForType method
minor formating changes.

llvm-svn: 25936

llvm-svn: 25932

llvm-svn: 25930

llvm-svn: 25929

llvm-svn: 25928

llvm-svn: 25925

llvm-svn: 25923

llvm-svn: 25921

llvm-svn: 25918

llvm-svn: 25916

llvm-svn: 25915

llvm-svn: 25914

Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place.  Other methods should also be moved if anyoneis interested. :)

llvm-svn: 25913

llvm-svn: 25911

llvm-svn: 25910