This should be the minimum set of functions that could possibly need it.

llvm-svn: 116978

llvm-svn: 116972

types are no longer Legal on X86, we don't need it.
No functional change.  8499854.

llvm-svn: 116947

llvm-svn: 116932

erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.

llvm-svn: 116845

is", which breaks some nightly tests.

llvm-svn: 116816

llvm-svn: 116801

llvm-svn: 116800

  "long latency" enough to hoist even if it may increase spilling. Reloading
  a value from spill slot is often cheaper than performing an expensive
  computation in the loop. For X86, that means machine LICM will hoist
  SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
  instructions.
- Enable register pressure aware machine LICM by default.

llvm-svn: 116781

word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes.  This is again for use just with assembly source for llvm-mc .

llvm-svn: 116773

llvm-svn: 116728

be more complete.  These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files.  Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added.  Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records.  More missing instructions will be coming.

llvm-svn: 116716

single object format can be shared.

This also adds support for

mov zed+(bar-foo), %eax

on ELF and COFF targets.

llvm-svn: 116675

if any floating point arguments are passed to an external function.

llvm-svn: 116665

immediates instead of 8 bits ones.

llvm-svn: 116410

8 bit constants can be used.

llvm-svn: 116403

Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457.

llvm-svn: 116368

that says what why what we just asserted is wrong.

llvm-svn: 116333

llvm-svn: 116323

llvm-svn: 116319

The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

llvm-svn: 116314

llvm-svn: 116214

llvm-svn: 116188

llvm-svn: 116177

llvm-svn: 116174

llvm-svn: 116173

llvm-svn: 116149

the add/or xform.  The JIT isn't mcized yet, boo.

This fixes Olden/voronoi, bh and a ton of other stuff that
uses the jit.

llvm-svn: 116125

llvm-svn: 116124

llvm-svn: 116083

llvm-svn: 116063

Small patch to restore home register stack space allocation for the Win64 case.  Add test case.  This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.

llvm-svn: 116056

the i8 versions of instructions in some cases.  In test6, we started 
generating:

	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
                                        ## <MCInst #478 CMP64mi32
                                        ##  <MCOperand Reg:114>
                                        ##  <MCOperand Imm:1>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:-8>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:0>>

instead of:

	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
                                        ## <MCInst #479 CMP64mi8
                                        ##  <MCOperand Reg:114>
                                        ##  <MCOperand Imm:1>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:-8>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:0>>

Fix this and add some comments.

llvm-svn: 116053

reapply: reimplement the second half of the or/add optimization.  We should now

with no changes.  Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.

llvm-svn: 116040

"Reimplement (part of) the or -> add optimization.  Matching 'or' into 'add'"

With a critical fix: the add pseudos clobber EFLAGS.

llvm-svn: 116039

'add'", which seems to have broken just about everything.

llvm-svn: 116033

on r116007, which I am about to revert.

llvm-svn: 116032

which depends on r116007, which I am about to revert.

llvm-svn: 116031

only end up emitting LEA instead of OR.  If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.

Add some testcases that we emit "or" in cases where we used to produce
an "add".

llvm-svn: 116026

casing FsMOVAPDrr/FsMOVAPSrr.

llvm-svn: 116016