llvm-svn: 14541

llvm-svn: 14540

llvm-svn: 14539

llvm-svn: 14538

llvm-svn: 14537

llvm-svn: 14536

llvm-svn: 14535

Contributed by Vladimir Prus!

llvm-svn: 14534

llvm-svn: 14533

llvm-svn: 14532

llvm-svn: 14531

* Wrap long line

llvm-svn: 14530

llvm-svn: 14529

llvm-svn: 14528

llvm-svn: 14527

llvm-svn: 14525

any other data structures

llvm-svn: 14524

use them instead of a local LiveVariables numbering

llvm-svn: 14523

a LV private map

llvm-svn: 14522

mapping

llvm-svn: 14521

llvm-svn: 14520

the reverse mapping as well as the mapping from MBB->unsigned

llvm-svn: 14519

map.

llvm-svn: 14518

Also convert df_iterator -> df_ext_iterator for subsequent stuff I'm doing.

llvm-svn: 14517

llvm-svn: 14516

llvm-svn: 14515

not with a debug build?  Rather testrunner only caught it in that case.

llvm-svn: 14514

llvm-svn: 14513

llvm-svn: 14512

* Congregate more branch-and-link opcodes together
* Mark FP, CPR, and special registers as volatile across calls

llvm-svn: 14511

* Define the condition register class

llvm-svn: 14510

* Only check for a register if we are sure the instruction has one allocated

llvm-svn: 14509

llvm-svn: 14508

llvm-svn: 14507

the PC in a code sequence for global variables.

llvm-svn: 14506

  for the function
* Registers aren't necessarily sequential wrt their enums, don't rely on it
  when emitting function arguments into sequential registers
* Remove X86-specific comments about AL/BL/AH/BH/EDX/etc
* Add an abort() for an unimplemented signed right shift
* The src operand for a GEP was never emitted!  Fixed.
* We can skip zero-valued GEP indices as they are no-ops.

"Hello, World!" now works.

llvm-svn: 14505

* Only increment labelNumber once, because it's used by both Load{hi,lo}Addr
* There is no .bss section on PowerPC
* Use .align 2 instead of other random numbers

llvm-svn: 14504

llvm-svn: 14503

llvm-svn: 14502

* Specify the isCall bit and caller-save registers for some call instrs

llvm-svn: 14501