llvm-svn: 31583

llvm-svn: 31569

llvm-svn: 31561

llvm-svn: 31549

  about whether the new base ptr would be live below the load/store. Let two
  address pass split it back to non-indexed ops.
- Minor tweaks / fixes.

llvm-svn: 31544

llvm-svn: 31543

This patch converts the old SHR instruction into two instructions,
AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not
dependent on the sign of their operands.

llvm-svn: 31542

llvm-svn: 31537

LBB1_57:        #bb207.i
        movl 72(%esp), %ecx
        movb (%ecx,%eax), %cl
        movl 80(%esp), %edx
        movb %cl, 1(%edx,%eax)
        incl %eax
        cmpl $143, %eax
        jne LBB1_57     #bb207.i
        jmp LBB1_64     #cond_next255.i

intead of:

LBB1_57:        #bb207.i
        movl 72(%esp), %ecx
        movb (%ecx,%eax), %cl
        movl 80(%esp), %edx
        movb %cl, 1(%edx,%eax)
        incl %eax
        cmpl $143, %eax
        je LBB1_64      #cond_next255.i
        jmp LBB1_57     #bb207.i

This eliminates a branch per iteration of the loop.  This hurted PPC
particularly, because the extra branch meant another dispatch group for each
iteration of the loop.

llvm-svn: 31530

llvm-svn: 31516

llvm-svn: 31514

llvm-svn: 31512

empty ranges.

2. Reorg how MachineDebugInfo maintains changes to debug labels.

3. Have dwarf writer use debug label info to simplify scopes and source line
coorespondence.

4. Revert the merging of compile units until I can get the bugs ironed out.

llvm-svn: 31507

by 40%, FreeBench/fourinarow by 20%, and many other programs 10-25%.

On PPC, this speeds up fourinarow by 18%, and probably other things as well.

llvm-svn: 31504

llvm-svn: 31500

llvm-svn: 31498

X86.  If happy, I'll enable this by default.

llvm-svn: 31493

llvm-svn: 31492

The low part goes in the first operand of expandop, not the second one.

llvm-svn: 31487

llvm-svn: 31478

NOTE: There doesn't seem to be consistency for whether a leading tab
is present in a section heading.

llvm-svn: 31475

llvm-svn: 31474

llvm-svn: 31473

llvm-svn: 31464

llvm-svn: 31459

llvm-svn: 31458

their scope are being deleted.  Workaround is to widen scope to full function.

llvm-svn: 31454

llvm-svn: 31453

there may be other def(s) apart from the use&def two-address operand. We need
to check if the register reuse for a use&def operand may conflicts with another
def. Provide a mean to recover from the conflict if it is detected when the
defs are processed later.

llvm-svn: 31439

llvm-svn: 31419

llvm-svn: 31417

llvm-svn: 31414

llvm-svn: 31413

llvm-svn: 31412

llvm-svn: 31410

llvm-svn: 31409

llvm-svn: 31408

llvm-svn: 31397

llvm-svn: 31387

1. Hash not quite right for DIEValues.

2. Not going to use Usage (no significant benefit.)

llvm-svn: 31384