for ARM to just check if a function has a FP to determine if it's safe
to simplify the stack adjustment pseudo ops prior to eliminating frame
indices. Allow targets to override the default behavior and does so for ARM
and Thumb2.

llvm-svn: 96634

strides in foreign loops. This helps locate reuse opportunities
with existing induction variables in foreign loops and reduces
the need for inserting new ones. This fixes rdar://7657764.

llvm-svn: 96629

a loop exit value, so that if a loop gets deleted, ScalarEvolution
isn't stick holding on to dangling SCEVAddRecExprs for that loop. This
fixes PR6339.

llvm-svn: 96626

llvm-svn: 96619

llvm-svn: 96616

llvm-svn: 96614

Moderate the weight given to very small intervals.

The spill weight given to new intervals created when spilling was not
normalized in the same way as the original spill weights calculated by
CalcSpillWeights. That meant that restored registers would tend to hang around
because they had a much higher spill weight that unspilled registers.

This improves the runtime of a few tests by up to 10%, and there are no
significant regressions.

llvm-svn: 96613

checking whether AnalyzeBranch disagrees with the CFG
directly, rather than looking for EH_LABEL instructions.
EH_LABEL instructions aren't always at the end of the
block, due to FP_REG_KILL and other things. This fixes
an infinite loop compiling MultiSource/Benchmarks/Bullet.

llvm-svn: 96611

llvm-svn: 96609

comes out as comments but will eventually generate DWARF.

llvm-svn: 96601

llvm-svn: 96591

llvm-svn: 96589

Russell Wallace.

llvm-svn: 96580

out by Russell Wallace.

llvm-svn: 96579

Also, have tools output -help-hidden rather than refer to --help-hidden,
for consistency, and likewise adjust documentation.  This doesn't change
every mention of --help, only those which seemed clearly safe.

llvm-svn: 96578

llvm-svn: 96574

Radar 7461718.

llvm-svn: 96572

of AI3ldsbpo, AI3ldhpo, and AI3ldshpo in ARMInstrFormats.td in the process.

llvm-svn: 96565

Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"

llvm-svn: 96556

llvm-svn: 96540

llvm-svn: 96532

since it has no pattern, there's not much point in distinguishing an "N2VS"
class for intrinsics anyway.

llvm-svn: 96525

A8.6.30

llvm-svn: 96523

* Use "S" abbreviation for scalar single FP registers in class and pattern
names, instead of keeping the "D" (for "double") abbreviation and tacking on
an "s" elsewhere in the name.
* Move the scalar single FP register classes and patterns to be more
consistent with other definitions in the file.
* Rename "VNEGf32d" definition to "VNEGfd" for consistency.
* Deleted the N2VDIntsPat pattern; N2VSPat is good enough.

llvm-svn: 96521

B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the
specified address and the following word respectively.

llvm-svn: 96519

Make the non-temporal bit "significant" in MemSDNodes so they aren't
CSE'd or otherwise combined with temporal MemSDNodes.

llvm-svn: 96505

llvm-svn: 96504

llvm-svn: 96503

llvm-svn: 96496

"Fix and issue in SparcAsmPrinter where multiple identical .LLGETPCHn symbols could be emitted in the same file (it was uniqued by block number, but not by function number). "  Patch by Nathan Keynes!

llvm-svn: 96495

and add a sparc implementation that knows about delay slots.  Patch by
Nathan Keynes!

llvm-svn: 96492

llvm-svn: 96490

cloned functions.

llvm-svn: 96485

cases that are not part of the enum.

llvm-svn: 96477

with mangled names).

llvm-svn: 96465

Renamed PIC16FrameOverlay namespace to PIC16OVERLAY.
Renamed PIC16FrameOverlay class to PIC16Overlay.

llvm-svn: 96463

A8.6.18  BFI - Bitfield insert (Encoding A1)

llvm-svn: 96462

tblgen splatted code into the implementation.

llvm-svn: 96460

reverse engineering what they are.

llvm-svn: 96456

Hopefully, this will fix the remaining issues seen there.

llvm-svn: 96454