structure.

llvm-svn: 78581

llvm-svn: 78576

instead of syntactically as a string.  This means that it keeps track of the 
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and 
"attribute(section)", so we should now start getting errors about invalid 
section attributes from the compiler instead of the assembler on darwin.

Still todo: 
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
   S_GB_ZEROFILL segment type?

llvm-svn: 78547

 - We can now discriminate SUB32ri8 from SUB32ri, for example.

llvm-svn: 78530

classes for X86.

llvm-svn: 78524

 -2 FIXMEs.

llvm-svn: 78523

llvm-svn: 78511

bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.

New test.

llvm-svn: 78508

Also, redefined MatchRegisterName to just return the register value or a
sentinel, to simplify the generated code.

llvm-svn: 78504

since they are in 64 bit mode with i64immSExt32 imms. JIT is not affected since 
it handles both word absolute relocations in the same way

llvm-svn: 78479

 - This doesn't actually improve the algorithm (its still linear), but the
   generated (match) code is now fairly compact and table driven. Still need a
   generic string matcher.

 - The table still needs to be compressed, this is quite simple to do and should
   shrink it to under 16k.

 - This also simplifies and restructures the code to make the match classes more
   explicit, in anticipation of resolving ambiguities.

llvm-svn: 78461

error condition get trapped with an assert.

llvm-svn: 78449

llvm-svn: 78443

llvm-svn: 78411

llvm-svn: 78404

llvm-svn: 78381

i386-apple-darwin9. This presumably will get fixed once the generated code
improves.

llvm-svn: 78379

 - Still not very sane, but a least its not 60k lines on X86. :)

 - In terms of correctness, currently some things are hard wired for X86, and we
   still don't properly resolve ambiguities (this is ignoring the instructions
   we don't even match due to funny .td stuff or other corner cases).

The high level changes:
 1. Represent tokens which are significant for matching explicitly as separate
    operands. This uniformly handles not only the instruction mnemonic, but
    also 'signficiant' syntax like the '*' in "call * ...".

 2. Separate the matching of operands to an instruction from the construction of
    the MCInst. In theory this can be done during matching, but since the number
    of variations is small I think it makes sense to decompose the problems.

 3. Improved a few of the mechanisms to at least successfully flatten / tokenize
    the assembly strings for PowerPC and ARM.

 4. The comment at the top of AsmMatcherEmitter.cpp explains the approach I'm
    moving towards for handling ambiguous instructions. The high-bit is to infer
    a partial ordering of the operand classes (and force the user to specify one
    if we can't) and use that to resolve ambiguities.

llvm-svn: 78378

llvm-svn: 78299

by aggressive chain operand optimization. UpdateNodeOperands
does not modify the node in place if it would result in
a node identical to an existing node.

llvm-svn: 78297

llvm-svn: 78293

subtle bug with small code model.

llvm-svn: 78255

is a subset of the other, but both are subsets of GR32.

llvm-svn: 78250

llvm-svn: 78242

a superset relation. This code wants to test the regular superset
relation.

llvm-svn: 78236

llvm-svn: 78219

PR4572. A few tests have some minor code regressions due to different
coalescing.

llvm-svn: 78217

llvm-svn: 78207

a dirty hack and isn't need anymore since the last x86 code emitter patch)
- Add a target-dependent modifier to addend calculation
- Use R_X86_64_32S relocation for X86::reloc_absolute_word_sext
- Use getELFSectionFlags whenever possible
- fix getTextSection to use TLOF and emit the right text section 
- Handle global emission for static ctors, dtors and Type::PointerTyID
- Some minor fixes

llvm-svn: 78176

MMX arguments. This fixes PR4684.

llvm-svn: 78163

them in the verifier.

llvm-svn: 78160

Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.

This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.

This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.

llvm-svn: 78142

calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.

llvm-svn: 78137

for ELF to work.  
2) RIP addressing: Use SIB bytes for absolute relocations where RegBase=0, 
IndexReg=0.
3) The JIT can get the real address of cstpools and jmptables during
code emission, fix that for object code emission

llvm-svn: 78129

still get "intel syntax" instructions from llc with  
-x86-asm-syntax=intel

llvm-svn: 78103

the masm backend.  If anyone cares about masm in the future,
we'll have semantic sections it can hang off of.

llvm-svn: 78096

add new concrete versions for 1/2/4-byte mergable strings.

These are not actually created yet.

llvm-svn: 78055

llvm-svn: 78006

more step towards "semantics sections"

llvm-svn: 78002

code that I will be using shortly.

llvm-svn: 77983