llvm-svn: 91481

remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface.  It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.

llvm-svn: 91464

llvm-svn: 91434

llvm-svn: 91417

llvm-svn: 91410

llvm-svn: 91405

llvm-svn: 91381

llvm-svn: 91371

llvm-svn: 91362

between BR_JTr and STREXD.

llvm-svn: 91339

llvm-svn: 91333

llvm-svn: 91329

llvm-svn: 91327

llvm-svn: 91321

Here's the diagnostic from clang:

/Volumes/Data/dgregor/Projects/llvm/lib/Target/CppBackend/CPPBackend.cpp:989:23: warning: 'gv' is always NULL in this context
        printConstant(gv);
                      ^
1 diagnostic generated.

llvm-svn: 91318

llvm-svn: 91313

llvm-svn: 91310

llvm-svn: 91307

llvm-svn: 91305

llvm-svn: 91284

llvm-svn: 91274

llvm-svn: 91260

llvm-svn: 91232

llvm-svn: 91230

merging x >u 5 and x <s 20 because it's impossible to implement.

llvm-svn: 91228

llvm-svn: 91223

No testcase yet - it seems we're exposing generic codegen bugs.

llvm-svn: 91221

llvm-svn: 91220

llvm-svn: 91219

just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.

llvm-svn: 91200

Based on the patch by Brian Lucas!

llvm-svn: 91175

llvm-svn: 91158

memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around.

llvm-svn: 91150

This is used in some weird cases like general dynamic TLS model.
This fixes PR5723

llvm-svn: 91144

llvm-svn: 91143

llvm-svn: 91140

llvm-svn: 91104

llvm-svn: 91090

llvm-svn: 91053

Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.

llvm-svn: 91003