- Mar 15, 2007
-
-
Reid Spencer authored
llvm-svn: 35116
-
Reid Spencer authored
llvm-svn: 35115
-
Evan Cheng authored
llvm-svn: 35114
-
Reid Spencer authored
llvm-svn: 35113
-
Reid Spencer authored
last entry stored in the map could be retrieved for a given integer type. Propagating the sign information required an invasive change to ensure that all ValueRef (ValID) instances get the right sign information as well. Also, put in some assertions to ensure the RenameMap always gives us out the type that is expected. This fixes PR1256 and test/Assembler/2007-03-14-UgpradeLocalSignless.ll llvm-svn: 35112
-
Reid Spencer authored
Carry sign with ValID and make TypeInfo sortable (useful in a map). llvm-svn: 35111
-
Reid Spencer authored
llvm-svn: 35110
-
- Mar 14, 2007
-
-
Evan Cheng authored
it as a late BURR scheduling tie-breaker. Intuitively, it's good to push down instructions whose results are liveout so their long live ranges won't conflict with other values which are needed inside the BB. Further prioritize liveout instructions by the number of operands which are calculated within the BB. llvm-svn: 35109
-
Evan Cheng authored
llvm-svn: 35108
-
Evan Cheng authored
llvm-svn: 35107
-
Duncan Sands authored
type, not the source type. llvm-svn: 35106
-
Evan Cheng authored
llvm-svn: 35105
-
Evan Cheng authored
llvm-svn: 35104
-
Jim Laskey authored
llvm-svn: 35103
-
Jim Laskey authored
llvm-svn: 35102
-
Jim Laskey authored
llvm-svn: 35101
-
Jim Laskey authored
llvm-svn: 35100
-
Jeff Cohen authored
llvm-svn: 35099
-
Jeff Cohen authored
llvm-svn: 35098
-
Evan Cheng authored
llvm-svn: 35097
-
Evan Cheng authored
llvm-svn: 35096
-
Evan Cheng authored
llvm-svn: 35095
-
Zhou Sheng authored
llvm-svn: 35094
-
Zhou Sheng authored
llvm-svn: 35093
-
Evan Cheng authored
llvm-svn: 35091
-
Evan Cheng authored
llvm-svn: 35090
-
Evan Cheng authored
e.g. t1 = op t2, c1 t3 = op t4, c2 and the following instructions are both ready. t2 = op c3 t4 = op c4 Then schedule t2 = op first. i.e. t4 = op c4 t2 = op c3 t1 = op t2, c1 t3 = op t4, c2 This creates more short live intervals which work better with the register allocator. llvm-svn: 35089
-
- Mar 13, 2007
-
-
Evan Cheng authored
llvm-svn: 35088
-
Evan Cheng authored
llvm-svn: 35087
-
Evan Cheng authored
llvm-svn: 35086
-
Duncan Sands authored
llvm-svn: 35084
-
Nicolas Geoffray authored
llvm-svn: 35083
-
Chris Lattner authored
Fix PR1244 and Transforms/InstCombine/2007-03-13-CompareMerge.ll llvm-svn: 35082
-
Chris Lattner authored
llvm-svn: 35081
-
Zhou Sheng authored
"APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth)", to handle ShiftAmt == BitWidth situation, use zextOrCopy() instead of zext(). llvm-svn: 35080
-
Zhou Sheng authored
llvm-svn: 35079
-
Zhou Sheng authored
1. Ensure VTy, KnownOne and KnownZero have same bitwidth. 2. Make code more efficient. llvm-svn: 35078
-
Evan Cheng authored
llvm-svn: 35077
-
Evan Cheng authored
More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale. llvm-svn: 35076
-
Evan Cheng authored
llvm-svn: 35075
-