- Feb 25, 2014
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Logan Chien authored
The function with uwtable attribute might be visited by the stack unwinder, thus the link register should be considered as clobbered after the execution of the branch and link instruction (i.e. the definition of the machine instruction can't be ignored) even when the callee function are marked with noreturn. llvm-svn: 202165
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Richard Osborne authored
The behaviour of the XCore's instruction buffer means that the performance of the same code sequence can differ depending on whether it starts at a 4 byte aligned address or not. Since we don't model the instruction buffer in the backend we have no way of knowing for sure if it is beneficial to word align a specific function. However, in the absence of precise modelling, it is better on balance to word align functions because: * It makes a fetch-nop while executing the prologue slightly less likely. * If we don't word align functions then a small perturbation in one function can have a dramatic knock on effect. If the size of the function changes it might change the alignment and therefore the performance of all the functions that happen to follow it in the binary. This butterfly effect makes it harder to reason about and measure the performance of code. llvm-svn: 202163
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Rafael Espindola authored
llvm-svn: 202157
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Rafael Espindola authored
llvm-svn: 202155
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Chandler Carruth authored
just "load". This helps avoid pointless de-duping with order-sensitive numbers as we already have unique names from the original load. It also makes the resulting IR quite a bit easier to read. llvm-svn: 202140
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Chandler Carruth authored
the pointer adjustment code. This is the primary code path that creates totally new instructions in SROA and being able to lump them based on the pointer value's name for which they were created causes *significantly* fewer name collisions and general noise in the debug output. This is particularly significant because it is making it much harder to track down instability in the output of SROA, as name de-duplication is a totally harmless form of instability that gets in the way of seeing real problems. The new fancy naming scheme tries to dig out the root "pre-SROA" name for pointer values and associate that all the way through the pointer formation instructions. Digging out the root is important to prevent the multiple iterative rounds of SROA from just layering too much cruft on top of cruft here. We already track the layers of SROAs iteration in the alloca name prefix. We don't need to duplicate it here. Should have no functionality change, and shouldn't have any really measurable impact on NDEBUG builds, as most of the complex logic is debug-only. llvm-svn: 202139
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Chandler Carruth authored
PHI-pointer builder, just copy the builder and clobber the obvious fields. llvm-svn: 202136
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Chandler Carruth authored
using OldPtr more heavily. Lots of this code was written before the rewriter had an OldPtr member setup ahead of time. There are already asserts in place that should ensure this doesn't change any functionality. llvm-svn: 202135
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Chandler Carruth authored
llvm-svn: 202134
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Nico Rieck authored
llvm-svn: 202130
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Chandler Carruth authored
the break statement, not just think it to yourself.... No idea how this worked at all, much less survived most bots, my bootstrap, and some bot bootstraps! The Polly one didn't survive, and this was filed as PR18959. I don't have a reduced test case and honestly I'm not seeing the need. What we probably need here are better asserts / debug-build behavior in SmallPtrSet so that this madness doesn't make it so far. llvm-svn: 202129
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Alexey Samsonov authored
llvm-svn: 202119
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Alp Toker authored
llvm-svn: 202107
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Chandler Carruth authored
sorting it. This helps uncover latent reliance on the original ordering which aren't guaranteed to be preserved by std::sort (but often are), and which are based on the use-def chain orderings which also aren't (technically) guaranteed. Only available in C++11 debug builds, and behind a flag to prevent noise at the moment, but this is generally useful so figured I'd put it in the tree rather than keeping it out-of-tree. llvm-svn: 202106
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Chandler Carruth authored
the destination operand or source operand of a memmove. It so happens that it was impossible for SROA to try to rewrite self-memmove where the operands are *identical*, because either such a think is volatile (and we don't rewrite) or it is non-volatile, and we don't even register it as a use of the alloca. However, making the 'IsDest' test *rely* on this subtle fact is... Very confusing for the reader. We should use the direct and readily available test of the Use* which gives us concrete information about which operand is being rewritten. No functionality changed, I hope! ;] llvm-svn: 202103
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Nick Lewycky authored
llvm-svn: 202096
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Chandler Carruth authored
ordering. The fundamental problem that we're hitting here is that the use-def chain ordering is *itself* not a stable thing to be relying on in the rewriting for SROA. Further, we use a non-stable sort over the slices to arrange them based on the section of the alloca they're operating on. With a debugging STL implementation (or different implementations in stage2 and stage3) this can cause stage2 != stage3. The specific aspect of this problem fixed in this commit deals with the rewriting and load-speculation around PHIs and Selects. This, like many other aspects of the use-rewriting in SROA, is really part of the "strong SSA-formation" that is doen by SROA where it works very hard to canonicalize loads and stores in *just* the right way to satisfy the needs of mem2reg[1]. When we have a select (or a PHI) with 2 uses of the same alloca, we test that loads downstream of the select are speculatable around it twice. If only one of the operands to the select needs to be rewritten, then if we get lucky we rewrite that one first and the select is immediately speculatable. This can cause the order of operand visitation, and thus the order of slices to be rewritten, to change an alloca from promotable to non-promotable and vice versa. The fix is to defer all of the speculation until *after* the rewrite phase is done. Once we've rewritten everything, we can accurately test for whether speculation will work (once, instead of twice!) and the order ceases to matter. This also happens to simplify the other subtlety of speculation -- we need to *not* speculate anything unless the result of speculating will make the alloca fully promotable by mem2reg. I had a previous attempt at simplifying this, but it was still pretty horrible. There is actually already a *really* nice test case for this in basictest.ll, but on multiple STL implementations and inputs, we just got "lucky". Fortunately, the test case is very small and we can essentially build it in exactly the opposite way to get reasonable coverage in both directions even from normal STL implementations. llvm-svn: 202092
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David Blaikie authored
llvm-svn: 202091
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Rafael Espindola authored
No functionality change. Just reduces the noise of an upcoming patch. llvm-svn: 202087
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- Feb 24, 2014
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Albrecht Kadlec authored
llvm-svn: 202084
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Matt Arsenault authored
llvm-svn: 202080
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Matt Arsenault authored
Does not yet include larger part required to match v_mad_i64_i32 / v_mad_u64_u32. llvm-svn: 202077
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Matt Arsenault authored
The check is clearer as southern islands or later, rather than checking for later than northern islands. llvm-svn: 202076
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Matt Arsenault authored
llvm-svn: 202075
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Matt Arsenault authored
llvm-svn: 202074
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Matt Arsenault authored
llvm-svn: 202073
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Arnold Schwaighofer authored
Vectorize sequential stores of a broadcasted value. 5% on eon. radar://16124699 llvm-svn: 202067
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Quentin Colombet authored
The patch defines new or refines existing generic scheduling classes to match the behavior of the SSE instructions. It also maps those scheduling classes on the related SSE instructions. <rdar://problem/15607571> llvm-svn: 202065
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Roman Divacky authored
llvm-svn: 202057
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Rafael Espindola authored
After this I will set the default back to F_None. The advantage is that before this patch forgetting to set F_Binary would corrupt a file on windows. Forgetting to set F_Text produces one that cannot be read in notepad, which is a better failure mode :-) llvm-svn: 202052
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Arnold Schwaighofer authored
During the LTO phase LICM will move loop invariant global variables out of loops (informed by GlobalModRef). This makes more loops countable presenting opportunity for the loop vectorizer. Adding the loop vectorizer improves some TSVC benchmarks and twolf/ref dataset (5%) on x86-64. radar://15970632 llvm-svn: 202051
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Rafael Espindola authored
This will make it easier to switch the default to being binary files. llvm-svn: 202042
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Kostya Serebryany authored
[asan] simplify the code that compute the shadow offset; get rid of two internal flags that allowed to override it. The tests pass, but still this change might break asan on some platform not covered by tests. If you see this, please submit a fix with a test. llvm-svn: 202033
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Christian Pirker authored
llvm-svn: 202024
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Elena Demikhovsky authored
llvm-svn: 202015
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Rafael Espindola authored
The only extra bit of functionality that had to be exposed for this be be implemented in Path.cpp is opening a file in rw mode. llvm-svn: 202005
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Rafael Espindola authored
llvm-svn: 202001
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Saleem Abdulrasool authored
The .error directive is similar to .err in that it will halt assembly if it is evaluated for assembly. However, it permits a user supplied message to be rendered. llvm-svn: 201999
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Saleem Abdulrasool authored
The .ifeqs directive assembles the following code if the quoted string parameters are equal. The strings must be quoted using double quotes. llvm-svn: 201998
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- Feb 23, 2014
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Benjamin Kramer authored
llvm-svn: 201994
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