MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form.

llvm-svn: 110794

llvm-svn: 110793

llvm-svn: 110792

llvm-mc: Add -show-inst-operands, for dumping the parsed instruction representation before matching.

llvm-svn: 110791

llvm-svn: 110790

llvm-svn: 110789

llvm-svn: 110788

llvm-svn: 110787

instructions: dmb, dsb, isb, msr, and mrs.

llvm-svn: 110786

  memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.

llvm-svn: 110785

llvm-svn: 110783

llvm-svn: 110782

for some reason they have a very odd MCInst form where the operands overlap, but
I haven't dug in to find out why yet.

llvm-svn: 110781

llvm-svn: 110780

llvm-svn: 110779

llvm-svn: 110778

llvm-svn: 110772

Remove AVX 256-bit unpack and interleave intrinsics now that clang is using __builtin_shufflevector for those

llvm-svn: 110769

llvm-svn: 110767

llvm-svn: 110765

llvm-svn: 110763

llvm-svn: 110762

llvm-svn: 110761

llvm-svn: 110759

make any assumptions about when the two conditions will agree on when
to permit the loop to exit. This fixes PR7845.

llvm-svn: 110758

from inline assembly, except in cases where they had already been seen (in which
case they would get added twice).
 - I can't see how this ever worked...

llvm-svn: 110757

llvm-svn: 110756

(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754

llvm-config.h are included.

This is the cmake counterpart of r110547. See bug #7809.

llvm-svn: 110753

llvm-svn: 110752

llvm-svn: 110751

llvm-svn: 110750

llvm-svn: 110748

llvm-svn: 110745

Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.

This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.

llvm-svn: 110744

create constraints from comparisons other than eq/neq.

llvm-svn: 110742

llvm-svn: 110739

llvm-svn: 110737

llvm-svn: 110735

patterns generated by clang for transpose of a matrix in generic vectors.  This is made
of two parts:

1) Propagating vector extracts of hi/lo half into their users
2) Recognizing an insertion of even elements followed by the odd elements as an unpack.

Testcase to come, but this shrinks the # of shuffle instructions generated on x86 from ~40 to the minimal 8.

llvm-svn: 110734