Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns.

llvm-svn: 171117

llvm-svn: 171115

LoopVectorizer: Optimize the vectorization of consecutive memory access when the iteration step is -1

llvm-svn: 171114

llvm-svn: 171113

llvm-svn: 171112

[asan] asan_allocator2: do not align the requested size to the redzone size (saves a bit more memory)

llvm-svn: 171111

Origin alignment is as high as the alignment of the corresponding application
location, but never less than 4.

llvm-svn: 171110

llvm-svn: 171109

llvm-svn: 171108

[asan] asan_allocator2: implement adaptive redzones. Now with asan_allocator2 allocations <= 48 bytes have 16 byte redzone, allocations of 48-96 bytes -- have 32 bytes redzone, etc (max redzone is 2048). If ASAN_OPTIONS=redzone=n is set, it changes the minimal redzone size

llvm-svn: 171107

llvm-svn: 171106

llvm-svn: 171105

llvm-svn: 171104

llvm-svn: 171103

llvm-svn: 171102

Reported by Yang Yongyong, thanks!

llvm-svn: 171101

Check for conflicting memory mappings before attempting to map shadow.
Helps avoid segfault on Linux with disabled ASLR.

llvm-svn: 171100

[asan] asan_allocator2: by default use the StackDepot to store the stack traces instead of storing them in the redzones

llvm-svn: 171099

llvm-svn: 171098

llvm-svn: 171097

llvm-svn: 171096

llvm-svn: 171095

llvm-svn: 171094

llvm-svn: 171093

Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions.

llvm-svn: 171092

llvm-svn: 171091

llvm-svn: 171090

[asan] asan_allocator2: store the user requested size in just 32 bits (larger sizes use metadata). This allows to put one more 32-bit field into the chunk header

llvm-svn: 171089

Template instantiation can set the canonical decl to used after subsequent
decls have been chained, so we have to check that too.

llvm-svn: 171088

Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN

llvm-svn: 171087

llvm-svn: 171086

llvm-svn: 171085

llvm-svn: 171084

llvm-svn: 171083

llvm-svn: 171082

Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment...

llvm-svn: 171081

Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX.

llvm-svn: 171080

For the time being this includes only some dummy test cases. Once the
generic implementation of the intrinsics cost function does something other
than assuming scalarization in all cases, or some target specializes the
interface, some real test cases can be added.

Also, for consistency, I changed the type of IID from unsigned to Intrinsic::ID
in a few other places.

llvm-svn: 171079

Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment.

llvm-svn: 171078

This fixes pr14691, which I think is a regression from r168519.

llvm-svn: 171077