For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias.

llvm-svn: 37351

llvm-svn: 37349

llvm-svn: 37342

llvm-svn: 37341

llvm-svn: 37340

llvm-svn: 37320

llvm-svn: 37308

llvm-svn: 37307

llvm-svn: 37289

for a target-dependent default with a command-line override; this way
should be generally usable.

llvm-svn: 37285

llvm-svn: 37275

llvm-svn: 37272

llvm-svn: 37271

llvm-svn: 37269

BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd.

llvm-svn: 37268

llvm-svn: 37266

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049845.html

llvm-svn: 37240

llvm-svn: 37239

llvm-svn: 37234

Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.

llvm-svn: 37199

llvm-svn: 37197

llvm-svn: 37194

llvm-svn: 37193

llvm-svn: 37192

in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm.  Ideally you would get cooperation
from the RA as well but this is not there yet.

llvm-svn: 37179

Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector.

llvm-svn: 37173

llvm-svn: 37172

cause other regressions.

llvm-svn: 37160

llvm-svn: 37159

llvm-svn: 37158

llvm-svn: 37154

llvm-svn: 37141

llvm-svn: 37139

llvm-svn: 37138

llvm-svn: 37125

llvm-svn: 37124

llvm-svn: 37123

llvm-svn: 37120

llvm-svn: 37119

Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.

llvm-svn: 37118