caused the a pushl instruction to be incorrectly encoding using only two bytes
of immediate, causing the following 2 instruction bytes to be part of the 32-bit
immediate value.  Also fixed the one byte form of push to be used when the
immediate would fit in a signed extended byte.  Lastly changed the names to not
include the 32 of PUSH32 since they actually push the size of the stack pointer.

llvm-svn: 102951

llvm-svn: 102941

llvm-svn: 102906

Remove the -enable-eh option which is only used by the JIT,
and replace it with -jit-enable-eh.

llvm-svn: 102865

llvm-svn: 102852

llvm-svn: 102836

llvm-svn: 102835

This should fix PR6603.

llvm-svn: 102834

changes before doing phi lowering for switches.

llvm-svn: 102809

llvm-svn: 102799

on the original variables, so it's easier to see what is being done
to which blocks.

llvm-svn: 102759

llvm-svn: 102730

Another sibcall bug. If caller and callee calling conventions differ, then it's only safe to do a tail call if the results are returned in the same way.

llvm-svn: 102683

print randomly in debug output.

llvm-svn: 102668

llvm-svn: 102657

	##DEBUG_VALUE: runOnMachineFunction:this <- RDI+0
	##DEBUG_VALUE: runOnMachineFunction:fn <- RSI+0
	##DEBUG_VALUE: DeadDefs <- undef ## SimpleRegisterCoalescing.cpp:2706
	##DEBUG_VALUE: getRegInfo:this <- [%rsp+$56]+$0
	##DEBUG_VALUE: getTarget:this <- [%rsp+$56]+$0

llvm-svn: 102655

should use esp / rsp to reference frame instead.

llvm-svn: 102596

llvm-svn: 102594

llvm-svn: 102577

Operand size override prefix to be part of their records.

llvm-svn: 102556

Add sizes non-floating point versions for the eh sjlj intrinsic expansions.

rdar://7895451

llvm-svn: 102526

instruction.

This instruction would crash the pass:

  INLINEASM <es:foo $0 $1>, 9, %FP0<kill>, 9, %FP0<kill>, 14, %EFLAGS<earlyclobber,def,dead>

Now it doesn't.

llvm-svn: 102509

llvm-svn: 102493

llvm-svn: 102488

llvm-svn: 102486

Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32).

llvm-svn: 102485

ForcedAlignBits argument, tweaking the single client of it.

llvm-svn: 102484

llvm-svn: 102477

llvm-svn: 102472

llvm-svn: 102467

llvm-svn: 102456

otherwise labels get incorrectly merged.  We handled this by emitting a 
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes.  Handle this by emitting a noop.  This
is more gross than it should be because arm/ppc are not fully mc'ized yet.

This fixes rdar://7908505

llvm-svn: 102400

Radar 7896289

llvm-svn: 102396

llvm-svn: 102373

DBG_VALUE, and a cautionary comment.

llvm-svn: 102371

llvm-svn: 102366

llvm-svn: 102326

llvm-svn: 102325

llvm-svn: 102324

- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.

llvm-svn: 102323