Skip to content
  1. Jun 30, 2008
    • Duncan Sands's avatar
      Revert the SelectionDAG optimization that makes · 1ae6ef83
      Duncan Sands authored
      it impossible to create a MERGE_VALUES node with
      only one result: sometimes it is useful to be able
      to create a node with only one result out of one of
      the results of a node with more than one result, for
      example because the new node will eventually be used
      to replace a one-result node using ReplaceAllUsesWith,
      cf X86TargetLowering::ExpandFP_TO_SINT.  On the other
      hand, most users of MERGE_VALUES don't need this and
      for them the optimization was valuable.  So add a new
      utility method getMergeValues for creating MERGE_VALUES
      nodes which by default performs the optimization.
      Change almost everywhere to use getMergeValues (and
      tidy some stuff up at the same time).
      
      llvm-svn: 52893
      1ae6ef83
  2. Jun 06, 2008
    • Duncan Sands's avatar
      Wrap MVT::ValueType in a struct to get type safety · 13237ac3
      Duncan Sands authored
      and better control the abstraction.  Rename the type
      to MVT.  To update out-of-tree patches, the main
      thing to do is to rename MVT::ValueType to MVT, and
      rewrite expressions like MVT::getSizeInBits(VT) in
      the form VT.getSizeInBits().  Use VT.getSimpleVT()
      to extract a MVT::SimpleValueType for use in switch
      statements (you will get an assert failure if VT is
      an extended value type - these shouldn't exist after
      type legalization).
      This results in a small speedup of codegen and no
      new testsuite failures (x86-64 linux).
      
      llvm-svn: 52044
      13237ac3
  3. May 14, 2008
  4. May 13, 2008
    • Sanjiv Gupta's avatar
      Adding files for Microchip's PIC16 target. · 4394c237
      Sanjiv Gupta authored
      A brief description about PIC16:
      ===============================
      PIC16 is an 8-bit microcontroller with only one 8-bit register which is the 
      accumulator. All arithmetic/load/store operations are 8-bit only.
      The architecture has two address spaces: program and data. The program memory 
      is divided into 2K pages and the data memory is divided into banks of 128 byte, with only 80 usable bytes, resulting in an non-contiguous data memory. 
      
      It supports direct data memory access (by specifying the address as part of the instruction) and indirect data and program memory access (in an unorthodox fashion which utilize a 16 bit pointer register). 
      
      Two classes of registers exist: (8-bit class which is only one
      accumulator) (16-bit class, which contains one or more 16 bit
      pointer(s))
      
      llvm-svn: 51027
      4394c237
Loading