llvm-svn: 171398

into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

llvm-svn: 171366

llvm-svn: 171356

llvm-svn: 171355

llvm-svn: 171352

llvm-svn: 171351

llvm-svn: 171340

llvm-svn: 171339

llvm-svn: 171338

llvm-svn: 171337

Use packed instead of scalar itineraries for SSE1/2 SQRTPS/PD, RCPPS, and RSQRTPS. VEX-encoded forms already use packed.

llvm-svn: 171336

llvm-svn: 171257

llvm-svn: 171256

directly.

This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.

llvm-svn: 171253

Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those.

llvm-svn: 171237

llvm-svn: 171229

Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled.

llvm-svn: 171227

llvm-svn: 171226

llvm-svn: 171180

llvm-svn: 171179

AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend.

llvm-svn: 171178

llvm-svn: 171172

llvm-svn: 171171

llvm-svn: 171170

llvm-svn: 171166

register. In most cases we actually compare or select YMM-sized registers
and mixing the two types creates horrible code. This commit optimizes
some of the transition sequences.

PR14657.

llvm-svn: 171148

The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization
and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps.
No new testcase because the original testcases still work.

llvm-svn: 171146

llvm-svn: 171143

Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again.

llvm-svn: 171141

Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation.

llvm-svn: 171137

llvm-svn: 171136

llvm-svn: 171130

Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them.

llvm-svn: 171128

Fix operands and encoding form for ARPL instruction. Register form had  and  reversed. Memory form writes memory, but was marked as MRMSrcMem.

llvm-svn: 171123

llvm-svn: 171122

llvm-svn: 171121

Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier.

llvm-svn: 171118

Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns.

llvm-svn: 171117

llvm-svn: 171103

llvm-svn: 171102