llvm-svn: 146725

llvm-svn: 146724

No need for an explicit test case for an unsupported combination of options.

llvm-svn: 146721

llvm-svn: 146718

llvm-svn: 146714

llvm-svn: 146713

properly initializing the target infos. I decided it wasn't worth linking them
in for this, so just switched back to using the Makefile variable for now. We
can reconsider later if we ever get pluggable targets.

llvm-svn: 146711

llvm-svn: 146710

Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly.  PR11586.

llvm-svn: 146709

llvm-svn: 146708

library names in line with those used by CMake.
 - Patch by Johannes Obermayr, with tweaks by me.

llvm-svn: 146706

llvm-svn: 146702

Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value.  (This is just to be safe; I don't think this actually causes any issues in practice.)

llvm-svn: 146700

llvm-svn: 146699

[asan] add the name of the module to the description of a global variable. This improves the readability of global-buffer-overflow reports.

llvm-svn: 146698

llvm-svn: 146692

llvm-svn: 146691

The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.

llvm-svn: 146690

Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146689

[asan] fix a bug (issue 19) where dlclose and the following mmap caused a false positive. compiler part.

llvm-svn: 146688

llvm-svn: 146686

llvm-svn: 146685

Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146684

llvm-svn: 146682

llvm-svn: 146678

llvm-svn: 146675

llvm-svn: 146674

Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>.

llvm-svn: 146671

Patch by Kyriakos Georgiou!

llvm-svn: 146670

llvm-svn: 146666

llvm-svn: 146665

llvm-svn: 146664

The function TRI::getCommonSubClass(A, B) returns the largest common
sub-class of the register classes A and B.  This patch teaches TableGen
to synthesize sub-classes such that the answer is always maximal.

In other words, every register that is in both A and B will also be
present in getCommonSubClass(A, B).

This introduces these synthetic register classes:

ARM:
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    tGPR_and_tcGPR
    hGPR_and_tcGPR

X86:
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR64_NOSP_and_GR64_TC
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_TC
    GR32_NOAX_and_GR32_NOSP
    GR64_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_ABCD_and_GR32_NOAX
    GR64_ABCD_and_GR64_TC
    GR32_NOAX_and_GR32_TC
    GR32_AD_and_GR32_NOAX

Other targets are unaffected.

llvm-svn: 146657

Patch by Kyriakos Georgiou.

llvm-svn: 146656

llvm-svn: 146642

llvm-svn: 146639

Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570.

llvm-svn: 146630

llvm-svn: 146627

rdar://10566486

llvm-svn: 146625

These can be reduced to "~cond & x" or "~cond | x"

llvm-svn: 146624