llvm-svn: 91489

Will reapply with a fix when I get a chance.

llvm-svn: 91486

in local register allocator.  If a reg-reg copy has a phys reg
input and a virt reg output, and this is the last use of the phys
reg, assign the phys reg to the virt reg.  If a reg-reg copy has
a phys reg output and we need to reload its spilled input, reload
it directly into the phys reg than passing it through another reg.

Following 76208, there is sometimes no dependency between the def of
a phys reg and its use; this creates a window where that phys reg
can be used for spilling (this is true in linear scan also).  This
is bad and needs to be fixed a better way, although 76208 works too
well in practice to be reverted.  However, there should normally be
no spilling within inline asm blocks.  The patch here goes a long way
towards making this actually be true.

llvm-svn: 91485

llvm-svn: 91481

enclosing namespace.  Caught by clang++.

llvm-svn: 91480

llvm-svn: 91479

llvm-svn: 91477

llvm-svn: 91475

remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface.  It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.

llvm-svn: 91464

llvm-svn: 91463

found last time.  Instead of trying to modify the IR while iterating over it,
I've change it to keep a list of WeakVH references to dead instructions, and
then delete those instructions later.  I also added some special case code to
detect and handle the situation when both operands of a memcpy intrinsic are
referencing the same alloca.

llvm-svn: 91459

llvm-svn: 91458

llvm-svn: 91448

real data, not metadata) and fix DbgInfoPrinter to not abuse
GetConstantStringInfo.

llvm-svn: 91444

llvm-svn: 91442

llvm-svn: 91440

llvm-svn: 91438

llvm-svn: 91434

llvm-svn: 91432

llvm-svn: 91428

1. Use std::equal instead of reinventing it.
2. don't run dtors in destroy_range if element is pod-like.
3. Use isPodLike to decide between memcpy/uninitialized_copy 
   instead of is_class.  isPodLike is more generous in some cases.

llvm-svn: 91427

up into the non-templated SmallVectorBase class.

llvm-svn: 91426

llvm-svn: 91425

llvm-svn: 91423

isPodLike type trait.  This is a generally useful type trait for
more than just DenseMap, and we really care about whether something
acts like a pod, not whether it really is a pod.

llvm-svn: 91421

llvm-svn: 91420

llvm-svn: 91419

llvm-svn: 91417

llvm-svn: 91416

llvm-svn: 91410

llvm-svn: 91407

llvm-svn: 91405

Checks that the code generated by 'tblgen --emit-llvmc' can be actually
compiled. Also fixes two bugs found in this way:

- forward_transformed_value didn't work with non-list arguments
- cl::ZeroOrOne is now called cl::Optional

llvm-svn: 91404

llvm-svn: 91403

llvm-svn: 91402

llvm-svn: 91401

1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest.
2. If the shift is a left shift, make sure the original shift cannot shift out bits.

llvm-svn: 91399

clang enforces it.

llvm-svn: 91397

stuff isn't used just yet.

We want to model the GCC `-fno-schedule-insns' and `-fno-schedule-insns2'
flags. The hypothesis is that the people who use these flags know what they are
doing, and have hand-optimized the C code to reduce latencies and other
conflicts.

The idea behind our scheme to turn off scheduling is to create a map "on the
side" during DAG generation. It will order the nodes by how they appeared in the
code. This map is then used during scheduling to get the ordering.

llvm-svn: 91392

Tail duplication should zap a copy it inserted for SSA update if the copy is the only use of its source.

llvm-svn: 91390