Commits · 1c6f0bb63e6d510513127e16775aec6a79ffdbf4 · Roger Ferrer / llvm-epi-0.8 · GitLab

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Sep 28, 2017
- Reverted r313993. · 1c6f0bb6
  Galina Kistanova authored Sep 27, 2017
  1c6f0bb6
Sep 27, 2017
- [MachineOutliner] AArch64: Avoid saving + restoring LR if possible · 4cf187b5
  Jessica Paquette authored Sep 27, 2017
  4cf187b5
- Revert r314249 "Recommit r314151 "[X86] Make all the NOREX CodeGenOnly... · c16a4729
  Craig Topper authored Sep 27, 2017
  c16a4729
- [CodeGen] Emit necessary .note sections for -fsplit-stack · dee2cf67
  Than McIntosh authored Sep 27, 2017
  dee2cf67
- [X86] In combineLoopSADPattern, pad result with zeros and use full size add... · 05f71dd0
  Craig Topper authored Sep 27, 2017
  05f71dd0
- [AArch64][Falkor] Ignore SP based loads in HW prefetch fixups. · c032b2be
  Geoff Berry authored Sep 27, 2017
  c032b2be
- [X86][SKX][KNL] Updated regression tests to use -mattr instead of -mcpu flag.NFC. · 87337a2b
  Gadi Haber authored Sep 27, 2017
  87337a2b
- X86 Tests: Unsigned saturation subtraction tests. NFC. · eb7a0bf8
  Zvi Rackover authored Sep 27, 2017
  eb7a0bf8
- [PowerPC] eliminate unconditional branch to the next instruction · ed1ffa49
  Hiroshi Inoue authored Sep 27, 2017
  ed1ffa49
- [X86][AVX] Improve (i4 bitcast (v4i1 x)) handling for 256-bit vector compare results. · 3b0d9e78
  Simon Pilgrim authored Sep 27, 2017
  3b0d9e78
- [X86] Fix SJLJ struct offsets for x86_64 · aa1533bf
  Martin Storsjo authored Sep 27, 2017
  aa1533bf
- [X86] Remove erroneous callsite offsetting in SJLJ landing pads · eccaf04e
  Martin Storsjo authored Sep 27, 2017
  eccaf04e
- [X86] Correct byte offsets and data types in a comment. NFC. · 233349fe
  Martin Storsjo authored Sep 27, 2017
  233349fe
- [X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors. · 177a3923
  Craig Topper authored Sep 27, 2017
  177a3923
- [X86] Add avx512bw command lines to the 256-bit vector idiv tests. · 31ccd472
  Craig Topper authored Sep 27, 2017
  31ccd472
Sep 26, 2017
- [AArch64][Falkor] Fix bug in falkor prefetcher fix pass. · bbfa246a
  Geoff Berry authored Sep 26, 2017
  bbfa246a
- [AArch64][Falkor] Fix correctness bug in falkor prefetcher fix pass and... · a4b2f5df
  Geoff Berry authored Sep 26, 2017
  a4b2f5df
- Recommit r314151 "[X86] Make all the NOREX CodeGenOnly instructions into... · 7f0eeb42
  Craig Topper authored Sep 26, 2017
  7f0eeb42
- [PowerPC] Reverting sequence of patches for elimination of comparison instructions · e22ebeab
  Nemanja Ivanovic authored Sep 26, 2017
  e22ebeab
- [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess... · 645f777e
  Michael Zuckerman authored Sep 26, 2017
  645f777e
- [NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins. · bab95c70
  Artem Belevich authored Sep 26, 2017
  bab95c70
- [X86] Add support for v16i32 UMUL_LOHI/SMUL_LOHI · f5191315
  Craig Topper authored Sep 26, 2017
  f5191315
- [x86] fix pr29061 · f191fdc3
  Coby Tayree authored Sep 26, 2017
  f191fdc3
- Revert "[X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos... · 4b2113a3
  Benjamin Kramer authored Sep 26, 2017
  4b2113a3
- [X86] Finishing broadcastf32x2 and broadcasti32x2 intrinsics lowering to IR. llvm side. · 0ecc984b
  Uriel Korach authored Sep 26, 2017
  0ecc984b
- [AVR] Fix the build after setting alignment to 1 in r314179 · f2c83670
  Dylan McKay authored Sep 26, 2017
  f2c83670
- Revert r312724 ("[ARM] Remove redundant vcvt patterns."). · edee9999
  Eli Friedman authored Sep 25, 2017
  edee9999
- X86: remove R12 from CSR on Windows x64 SwiftCC · 2e0d7231
  Saleem Abdulrasool authored Sep 25, 2017
  2e0d7231
Sep 25, 2017
- [ARM] Fix tests for vcvt+store to return void. · 48853741
  Eli Friedman authored Sep 25, 2017
  48853741
- [ARM] Add tests for vcvt followed by store. · 7961112d
  Eli Friedman authored Sep 25, 2017
  7961112d
- [ARM] Regenerate vcvt test checks. · 7404fad2
  Eli Friedman authored Sep 25, 2017
  7404fad2
- [X86] Don't select anyext GR32->GR64 to SUBREG_TO_REG. Use INSERT_SUBREG instead. · 5124a14d
  Craig Topper authored Sep 25, 2017
  5124a14d
- [X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos like the... · d830f276
  Craig Topper authored Sep 25, 2017
  d830f276
- Revert "[NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins.", rL314135. · d31d5e6a
  Justin Lebar authored Sep 25, 2017
  d31d5e6a
- [SelectionDAG] Teach simplifyDemandedBits to handle shifts by constant splat vectors · 5bc10ede
  Craig Topper authored Sep 25, 2017
  5bc10ede
- [NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins. · 9941ee95
  Artem Belevich authored Sep 25, 2017
  9941ee95
- ARM: Use the proper swifterror CSR list on platforms other than darwin · ae4de58a
  Arnold Schwaighofer authored Sep 25, 2017
  ae4de58a
- [DebugInfo] Sort the SDDbgValue list before assuming it is in IR order · 8898cd8d
  Reid Kleckner authored Sep 25, 2017
  8898cd8d
- [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess (VF8 stride 4): · 4a97df01
  Michael Zuckerman authored Sep 25, 2017
  4a97df01
- [PowerPC] Eliminate compares - add i64 sext/zext handling for SETLT/SETGT · f7bc9ce3
  Nemanja Ivanovic authored Sep 25, 2017
  f7bc9ce3