loadRegFromStackSlot. 

llvm-svn: 147235

llvm-svn: 147234

llvm-svn: 147232

llvm-svn: 147231

ARM targets with NEON units have access to aligned vector loads and
stores that are potentially faster than unaligned operations.

Add support for spilling the callee-saved NEON registers to an aligned
stack area using 16-byte aligned NEON loads and store.

This feature is off by default, controlled by an -align-neon-spills
command line option.

llvm-svn: 147211

My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo
instruction, but on Thumb1 some of those registers cannot be used.  This
caused massive failures on the testsuite when compiling for Thumb1.  While
fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp"
variant, and I realized that dispatchsetup needs the same thing, so I have
added that as well.

llvm-svn: 147204

llvm-svn: 147192

rdar://10558523

llvm-svn: 147189

Noticed by inspection; I don't have a testcase for this.

llvm-svn: 147188

llvm-svn: 147184

Fixes PR11214.

llvm-svn: 147180

The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.

Partial for: rdar://10558523

llvm-svn: 147170

llvm-svn: 147169

llvm-svn: 147158

it. It does need some some tests...

llvm-svn: 147154

Just treat it as-if the shift wasn't there at all. 'as' compatibility.

rdar://10604767

llvm-svn: 147153

llvm-svn: 147152

llvm-svn: 147151

llvm-svn: 147150

llvm-svn: 147133

llvm-svn: 147132

llvm-svn: 147129

llvm-svn: 147126

llvm-svn: 147124

llvm-svn: 147121

llvm-svn: 147119

ELF relocations.

Patch by Jack Carter.

llvm-svn: 147118

llvm-svn: 147117

llvm-svn: 147115

llvm-svn: 147109

llvm-svn: 147104

llvm-svn: 147103

llvm-svn: 147102

Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.

rdar://10611140

llvm-svn: 147100

Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

llvm-svn: 147096

llvm-svn: 147095

These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

llvm-svn: 147094

llvm-svn: 147071

llvm-svn: 147069

necessary.  Please chime in if I'm mistaken.

llvm-svn: 147065