For more information, see the accompanying clang patch.

llvm-svn: 111454

and optional def operands are handled in the backend support.

llvm-svn: 111220

instructions besides saturate instructions.  No functional changes.

llvm-svn: 111168

llvm-svn: 111149

llvm-svn: 111102

llvm-svn: 111094

llvm-svn: 111082

Apparently, this is now fixed in Clang.

llvm-svn: 111032

llvm-svn: 111007

Tested on Linux and Darwin; please add platform-specific XFAILs/mail me a bug
report if this still fails.

llvm-svn: 110998

the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.

llvm-svn: 110951

target specific parsers can adapt the TargetAsmParser to this.

llvm-svn: 110888

instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875

llvm-svn: 110789

llvm-svn: 110779

(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754

llvm-svn: 110748

llvm-svn: 110687

if-else statements, to hopefully support older pythons (PR7850).

llvm-svn: 110638

useful after all.

llvm-svn: 110531

Without this what was happening was:

* R3 is not marked as "used"
* ARM backend thinks it has to save it to the stack because of vaarg
* Offset computation correctly ignores it
* Offsets are wrong

llvm-svn: 110446

need the Compare flag after all.

--- Reverse-merging r109901 into '.':
U    include/llvm/Target/TargetInstrDesc.h
U    include/llvm/Target/Target.td
U    utils/TableGen/InstrInfoEmitter.cpp
U    utils/TableGen/CodeGenInstruction.cpp
U    utils/TableGen/CodeGenInstruction.h

llvm-svn: 110424

llvm-svn: 110422

llvm-svn: 110419

to IntrReadWriteArgMem, as it's for reading as well as writing.

llvm-svn: 110395

and add comments about major implemented features.

llvm-svn: 110215

alone, rather than just an exit code.

llvm-svn: 110208

llvm-svn: 110206

llvm-svn: 110205

llvm-svn: 110204

llvm-svn: 110203

it doesn't modify the exit code or the stdout contents, and so that it
doesn't clutter the output with "Command has output on stderr!".

llvm-svn: 110171

and same for stderr, to avoid clutter in the output.

llvm-svn: 110169

llvm-svn: 110168

llvm-svn: 110001

build and has the object build directory baked into it. This allows 'llvm-lit'
to properly find the information needed to run the test suite in all cases,
without requiring the user to have LLVM or 'lit' available in their PATH, for
example.

llvm-svn: 110000

llvm-svn: 109999

later to identify and possibly remove superfluous compare instructions -- those
that are testing for and setting a status flag that should already be set.

llvm-svn: 109901

llvm-svn: 109858

have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
  mls r0,r9,r0,sp
instead of:
  mov r2, sp
  mls r0, r9, r0, r2

This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.

PR7499

llvm-svn: 109842